A 43mW Bluetooth transceiver with -91dBm sensitivity

Abstract

As Bluetooth V1.1 [1] compliance is achieved by several solutions, the original low power objective re-emerges as a key factor for integration in portable devices. Since the standard -70dBm sensitivity was achieved with ease, commercial solutions have converged on a worst-case -80dBm sensitivity to attain longer reach from Class-2 output power (< 4mW) devices. This paper presents the second generation of a 1.8V Bluetooth transceiver [2]. Peak current consumption is 24mA for the receiver and 18mA for the transmitter at 6dBm output power.A prerequisite for low power operation is a low voltage supply. All the RF/analog circuitry is functional down to 1.65V. The digital section is designed to work at 1.3V, despite the high threshold voltages of the 0.5µm/3V CMOS backend. Architecture selection has a large impact on transceiver power consumption. For the transmitter, two-point closed-loop direct modulation is used to generate the 2-GFSK modulated carrier. The fractional-N deltasigma (fN-DS) synthesizer required to permit various crystal reference frequencies is reused to generate the low-frequency band of the modulated signal. The high-frequency band is realized by direct analog VCO frequency modulation. The receiver uses a low-IF heterodyne architecture to allow on-chip implementation of the analog channel filters. The GFSK demodulator is implemented in the digital domain for maximum flexibility. This allows power consumption reduction through on-chip digital supply voltage regulation.The receiver chain starts with a differential LNA with inductive degeneration. The LNA output drives an RF power detector whose output is quantized to 1-bit, with 5dB of hysteresis. Quadrature mixers downconvert the RF signal to a 1MHz IF. The mixers have two gain settings 12dB apart. The mixers gain mode can be set directly by the 1-bit RF detector output, or it can be set by the receiver controller based on the combined RF and IF RSSI level.Most of the receiver gain and selectivity is provided in the analog IF strip, which alternates complex bandpass filter (CBPF) stages with variable gain amplifiers (VGA). A solution based on filtering first followed by signal limiting was rejected due to the high power consumption required by a low noise, high dynamic range and high linearity filter preceding the limiting strip. Alternating filter and gain stages allows better trade-offs between noise figure and linearity for each stage, by progressively reducing the dynamic range as the signal level is amplified. A typical IF stage is shown in Fig. 5.3.1. The CBPF stage is based on transconductor-RC circuits and has third-order intermodulation products below -60dBc when exercised with two 125mV pp tones. Filter tuning is based on RC delay measurements. A peak detector (PkD) circuit measures the power of the signal at the output of the filter stage. The PkD output is quantized to a 3-bit word that controls the 8-level VGA. During the data packet, the VGA's are operated in "hold" mode, in which the previously sampled PkD outputs are stored and applie...

Low Power Impulse Radio Transceivers

“…Noncoherent detection schemes tend to be lower power. Adapted from ref [27,[28][29][30][31][32][33] for 80-85 in the figure and [34][35][36][37][38][39] for 106-111 in the figure Fig. 3.33 Schematic of non-coherent detection scheme Short transient decay times allow the receiver to be duty cycled to less than 0.1 % (10 ns in a 10 us period), yielding an average power consumption of ~ 12 µW in our 90 nm CMOS example, including leakage.…”

Realizing a CMOS RF Transceiver for Wireless Sensor Networks

“…Conventional transceiver architectures as shown in Fig.1 include heterodyne, zero-IF (intermediate-frequency), and low-IF conversion structure (P. S. Choi et al (2003), C. Cojocaru et al (2003), M. Valla et al (2005), Ilku-Nam et al (2003)), each having their own advantages and disadvantages. However, it becomes further challenging to meet all the specifications of many applications while keeping more competitiveness than the others.…”

“…The low-IF and zero-IF architectures can achieve much better performance at low-power consumption and are well suited for high integration. The concept of the low-IF (P. S. Choi et al (2003), C. Cojocaru et al (2003)) starts from the survey that all information necessary to separate the mirror frequency from the wanted frequency is available in the two low frequencies after quadrature conversion. This scheme can avoid the DC offset problem and eliminate IF SAW and image RF filters.…”

Design of Baseband Analog Chain with Optimum Allocation of Gain and Filter Rejection for WLAN Applications

“…Gain stage followed by filter stage relaxes filter noise requirements while demanding a high linearity amplifier. The use of alternating filter and gain stages allows a better trade-off to be obtained between the noise and linearity for each stage by progressively reducing the dynamic range as the signal level is amplified [5]. In this design, the total filter rejection of 90 dB at 40 MHz and unity gain of the filter stage are required.…”