A 45-&lt;inline-formula&gt; 
                     &lt;tex-math notation="LaTeX"&gt;$\mu$ &lt;/tex-math&gt;
                  &lt;/inline-formula&gt;W, 162.1-dBc/Hz FoM, 490-MHz Two-Stage Differential Ring VCO Without a Cross-Coupled Latch

Jung, Oh-Yong; Seok, Hyun-Gi; Dissanayake, Anjana; Lee, Sang‐Gug

doi:10.1109/tcsii.2017.2766674

Cited by 20 publications

(11 citation statements)

References 10 publications

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“…In [4]- [6], [8], [9], four stages are used to design the RVCO. In [3] and [7], five and two stages are used to…”

Section: Post-layout Simulation Resultsmentioning

confidence: 99%

“…1mW [8] design RVCO, respectively. The results shown for [4], [7]- [9], [14]- [16] are measured results, and [3], [5], [6] are from postlayout simulations. It is observed that the phase noise of the PRVCO is better than the architectures given in [3]- [9], [14]- [16].…”

Section: Post-layout Simulation Resultsmentioning

confidence: 99%

“…But the operating frequency range is lesser than the PRVCO. In [7], the power dissipation is lesser than PRVCO because it uses the 0.6 V supply voltage. But the operating frequency range of PRVCO is significantly better than RVCO presented in [7].…”

Section: Post-layout Simulation Resultsmentioning

confidence: 99%

“…In [7], the power dissipation is lesser than PRVCO because it uses the 0.6 V supply voltage. But the operating frequency range of PRVCO is significantly better than RVCO presented in [7]. In [14], bootstrap RVCO is presented for higher operating frequency, but the phase noise performance is poor.…”

Section: Post-layout Simulation Resultsmentioning

confidence: 99%

“…In [6], an Mayank Kumar Singh, Puneet Singh, Devarshi Mrinal Das, and Mahendra Sakare are with the Department of Electrical Engineering, Indian Institute of Technology Ropar, Rupnagar 140001, India (email: mayank.19eez0008@iitrpr.ac.in; puneet.19eez0003@iitrpr.ac.in; devarshi.das@iitrpr.ac.in; mahendra@iitrpr.ac.in) Naveen Kadayinti is with the Department of Electrical Engineering, Indian Institute of Technology Dharwad, India (email: naveen@iitdh.ac.in) RVCO using a feed-forward latch with dual loop topology to improve the operating frequency and phase noise is presented. In [7], an RC network-based delay cell is shown for low-power operation. It requires a larger area due to the capacitors with reduced operating frequency.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Frequency Range Enhancement in Differential Ring VCO while Maintaining Phase Noise Performance

SINGH¹,

Singh²,

Kadayinti³

et al. 2023

Preprint

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<p>This paper presents a differential delay cell-based ring voltage-controlled oscillator (RVCO). The proposed RVCO (PRVCO) introduces auxiliary charging and discharging paths in conventional ring VCO (CRVCO) that enhance the maximum operating frequency and frequency range. Adding auxiliary paths does not increase the maximum current in PRVCO within different time instants in one period compared to other available RVCOs. Thus, it maintains the phase noise performance. The post-layout simulations of the four-stage PRVCO were performed in 65nm CMOS technology with 1V supply voltage. The maximum operating frequency of the four-stage CRVCO, and PRVCO, are 585MHz and 3.2 GHz, respectively. The PRVCO improves the maximum operating frequency significantly compared to CRVCO. The PRVCO has a linear tuning range from 1.8 GHz to 3.2 GHz, which is 78% better than the CRVCO. The phase noise of the PRVCO is -103.8 dBc/Hz at an offset frequency of 1 MHz. The figure of merit (FoM) is improved by 11 dB compared to CRVCO in the same technology node of 65nm CMOS.</p>

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“…In [4]- [6], [8], [9], four stages are used to design the RVCO. In [3] and [7], five and two stages are used to…”

Section: Post-layout Simulation Resultsmentioning

confidence: 99%

Section: Post-layout Simulation Resultsmentioning

confidence: 99%

Section: Post-layout Simulation Resultsmentioning

confidence: 99%

Section: Post-layout Simulation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Frequency Range Enhancement in Differential Ring VCO while Maintaining Phase Noise Performance

SINGH¹,

Singh²,

Kadayinti³

et al. 2023

Preprint

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show abstract

A wide tuning range CMOS differential ring VCO using an active inductor for wireless applications

Alijani,

Javanmardi,

Abrishamifar

2024

Circuit Theory & Apps

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A differential ring voltage‐controlled oscillator (DRVCO) is proposed in this paper as one of the critical blocks in communication systems. It consists of four stages of delay cells connected in a chain, creating a ring structure with auxiliary path interconnections. The oscillation frequency of the DRVCO can be controlled by adjusting the tuning voltage that controls the charging current. To achieve the desired performance for wireless applications, the Wu active inductor, which is a low‐noise and high‐quality factor active inductor, is employed in each delay cell for the first time. Using an active inductor provides a wide tuning range and also allows for proper phase noise and low power consumption. The proposed circuit is designed and simulated using standard 180‐nm CMOS technology with a 1.8‐V voltage source (VDD). The circuit is designed to achieve a tuning range of 2.15 GHz with a center frequency oscillation of 2.745 GHz, over the control voltage variation of 1.4 V (0 to 1.4 V). To achieve the desired performance, the circuit consumes an average power of 1.99 mW. It achieves a phase noise of − 91.2 dBc/Hz at 1 MHz offset frequency, indicating effective noise suppression. The figure of merit (FoM) for the circuit is − 156.9 dBc/Hz, representing its overall performance. The final layout of the circuit estimates an area of 0.00072 mm2. Various analyses, including Monte–Carlo simulations, PVT (process, voltage, temperature) variation analysis, and other relevant analyses, have been performed to ensure the reliable performance of the proposed circuit.

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Modeling and Analysis of a Frequency-Locked Loop Based on Two-Stage Ring Voltage-Controlled Oscillator

Sun

Zhou

et al. 2021

Circuits Syst Signal Process

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A 45-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>W, 162.1-dBc/Hz FoM, 490-MHz Two-Stage Differential Ring VCO Without a Cross-Coupled Latch

Cited by 20 publications

References 10 publications

Frequency Range Enhancement in Differential Ring VCO while Maintaining Phase Noise Performance

Frequency Range Enhancement in Differential Ring VCO while Maintaining Phase Noise Performance

A wide tuning range CMOS differential ring VCO using an active inductor for wireless applications

Modeling and Analysis of a Frequency-Locked Loop Based on Two-Stage Ring Voltage-Controlled Oscillator

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