A 450 Mbit/s EPR4 PRML read/write channel
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As the difficulty in increasing areal recording densities rises, more attention is given to improvements available from advanced signal processing. A promising technique to achieve SNR improvement is the use of iterative decoding. Initial investigations of turbo codes for applications in recording channels have created a great deal of interest among researchers in both academia and industry over the past few years. A large number of publications have appeared in the areas of code design and ultimate code performance, but somewhat less attention has been paid to decoding architectures or to implementation and system issues. Although iterative decoders promise large gains over conventional PRML systems, they have not been used in commercial applications so far.Our thesis is that this situation is due, at least in part, to the difficulty in finding the optimum trade-off between performance and complexity/cost. Disk drive read/write channels have traditionally been very cost sensitive. The area of the silicon chip directly dictates its price, while power dissipation has to be low enough to allow for inexpensive packaging and system cooling. Historically, CMOS scaling has been used to allow more advanced signal processing at increased decoding speed, while the power and area stay roughly the same in each new technology generation. Thus, the challenge is to find the algorithm that achieves the best SNR performance at reasonably high speed while staying within these constraints.We screen the large number of choices initially available based on some quick, coarse analysis. For example, both BCJR and SOVA algorithms have been considered for the inner (channel) detector. It is generally recognized that any performance benefit that the BCJR possesses is more than offset by the large complexity penalty, so we consider here only the SOVA option. Iterative detectors based on convolutional codes are also recognized to be too complex to justify the extra performance they offer, so we limit this discussion to those based on simple parity checks:• Random Low-Density-Parity-Check (LDPC) code with rate 8/9 and column weight 3• Turbo Product Code (TPC) based on single parity checks, with sixteen 16×16 matrices, a precoder and a random interleaverIn order to place the results in context, we also include performance and complexity estimates for a simple 16-state Viterbi detector and for an advanced PRML channel with noise-prediction in the 32-state Viterbi trellis and paritybased post-processing, as described in [1]. Noise-predictive decoders with parity post-processing can be also used for complexity comparison: at the point of their introduction they occupied 1-2mm 2 of silicon area while dissipating less than 500mW.The iterative decoding algorithm is similar for the TPC and LDPC codes. The SOVA algorithm is used on the channel trellis, and the Message Passing Algorithm (MPA) is used for soft decoding of the TPC and LDPC codes. The decoding is established by iterating between the inner channel decoder and the outer decoder. The LDPC...
As the difficulty in increasing areal recording densities rises, more attention is given to improvements available from advanced signal processing. A promising technique to achieve SNR improvement is the use of iterative decoding. Initial investigations of turbo codes for applications in recording channels have created a great deal of interest among researchers in both academia and industry over the past few years. A large number of publications have appeared in the areas of code design and ultimate code performance, but somewhat less attention has been paid to decoding architectures or to implementation and system issues. Although iterative decoders promise large gains over conventional PRML systems, they have not been used in commercial applications so far.Our thesis is that this situation is due, at least in part, to the difficulty in finding the optimum trade-off between performance and complexity/cost. Disk drive read/write channels have traditionally been very cost sensitive. The area of the silicon chip directly dictates its price, while power dissipation has to be low enough to allow for inexpensive packaging and system cooling. Historically, CMOS scaling has been used to allow more advanced signal processing at increased decoding speed, while the power and area stay roughly the same in each new technology generation. Thus, the challenge is to find the algorithm that achieves the best SNR performance at reasonably high speed while staying within these constraints.We screen the large number of choices initially available based on some quick, coarse analysis. For example, both BCJR and SOVA algorithms have been considered for the inner (channel) detector. It is generally recognized that any performance benefit that the BCJR possesses is more than offset by the large complexity penalty, so we consider here only the SOVA option. Iterative detectors based on convolutional codes are also recognized to be too complex to justify the extra performance they offer, so we limit this discussion to those based on simple parity checks:• Random Low-Density-Parity-Check (LDPC) code with rate 8/9 and column weight 3• Turbo Product Code (TPC) based on single parity checks, with sixteen 16×16 matrices, a precoder and a random interleaverIn order to place the results in context, we also include performance and complexity estimates for a simple 16-state Viterbi detector and for an advanced PRML channel with noise-prediction in the 32-state Viterbi trellis and paritybased post-processing, as described in [1]. Noise-predictive decoders with parity post-processing can be also used for complexity comparison: at the point of their introduction they occupied 1-2mm 2 of silicon area while dissipating less than 500mW.The iterative decoding algorithm is similar for the TPC and LDPC codes. The SOVA algorithm is used on the channel trellis, and the Message Passing Algorithm (MPA) is used for soft decoding of the TPC and LDPC codes. The decoding is established by iterating between the inner channel decoder and the outer decoder. The LDPC...
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