A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding F<sub>MAX</sub> tracking

Wilson, Robin; Beigné, Edith; Flatresse, Philippe; Valentian, Alexandre; Abouzeid, Fady; Benoist, T.; Bernard, Christian; Bernard, Sebastien; Billoint, Olivier; Clerc, Sylvain; Giraud, B.; Grover, Anuj; Coz, Julien Le; Panades, Ivan Miro; Noël, Jean-Philippe; Pelloux-Prayer, Bertrand; Roché, Philippe; Thomas, Olivier; Thonnart, Yvain; Turgis, David; Clermidy, Fabien; Magarshack, Philippe

doi:10.1109/isscc.2014.6757509

Cited by 34 publications

(11 citation statements)

References 2 publications

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“…Figure 5 icated to complex arithmetic functions and two dedicated operators, a cordic/divider and a compare/select [17]. The measurements are performed for a constant temperature T • by executing the same task with a constant average activity A for each measurement for a triplet (F , V dd , V bb ).…”

Section: Results On a Fd-soi Circuitmentioning

confidence: 99%

Power management through DVFS and dynamic body biasing in FD-SOI circuits

Akgul

Puschini

Lesecq

et al. 2014

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

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The emerging SOI technologies provide an increased body bias range compared to traditional bulk technologies, opening new opportunities. From the power management perspective, a new degree of freedom is added to the supply voltage and clock frequency variation, increasing the complexity of the power optimization problem. In this paper, a method is proposed to manage the power consumed in an FD-SOI circuit through supply and body bias voltages, and clock frequency variation. Results for a Digital Signal Processor in STMicroelectronics 28nm FD-SOI technology show that the power reduction ratio can reach 17%.

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Section: Results On a Fd-soi Circuitmentioning

confidence: 99%

Power management through DVFS and dynamic body biasing in FD-SOI circuits

Akgul

Puschini

Lesecq

et al. 2014

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

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“…So, solely shifting the V BB value in function of the environment temperature could allow us to obtain a more desired (self-controlled) behavior, and then, present a temperature insensitive system. Note that, this V BB management does not introduce too much system complexity [17].…”

Section: Relevance Of Environment Temperaturementioning

confidence: 97%

FDSOI Suitability for Asynchronous Circuits at Sub-V_T

et al. 2015

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In this work, we explore the benefits of Fully Depleted Silicon-onInsulator (FDSOI) devices to implement full-adders focused to operate at sub-threshold level. Their design based on asynchronous proposal shows lower energy consumption than their synchronous counterparts. Afterwards, the use of the FDSOI back-gate bias (V BB ) allows an enhancement of sub-threshold circuit behavior, in contrast of other technology proposals. Their proper management could provide a temperature insensitive circuit behavior and larger variability robustness.

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“…A dynamic tuning of performance is of interest for a large range of design targets, ranging from logic gates [Noel et al 2011] to embedded memories [Thomas et al 2012]. Such techniques were recently employed in a low-power digital signal processing (DSP) design [Wilson et al 2014], demonstrating the large interest in the approach.…”

Section: Ultra-wide-voltage-range Design Through Additional Electrostmentioning

confidence: 99%

A Survey on Low-Power Techniques with Emerging Technologies

Gaillardon

Beigné

Lesecq

et al. 2015

J. Emerg. Technol. Comput. Syst.

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Nowadays, power consumption is one of the main limitations of electronic systems. In this context, novel and emerging devices provide new opportunities to extend the trend toward low-power design. In this survey article, we present a transversal survey on energy-efficient techniques ranging from devices to architectures. The actual trends of device research, with fully depleted planar devices, tri-gate geometries, and gateall-around structures, allows us to reach an increasingly higher level of performance while reducing the associated power. In addition, beyond the simple device property enhancements, emerging devices also lead to innovations at the circuit and architectural levels. In particular, devices whose properties can be tuned through additional terminals enable a fine and dynamic control of device threshold. They also enable designers to realize logic gates and to implement power-related techniques in a compact way unreachable to standard technologies. These innovations reduce power consumption at the gate level and unlock new means of actuation in architectural solutions like adaptive voltage and frequency scaling.

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A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding F_MAX tracking

Cited by 34 publications

References 2 publications

Power management through DVFS and dynamic body biasing in FD-SOI circuits

Power management through DVFS and dynamic body biasing in FD-SOI circuits

FDSOI Suitability for Asynchronous Circuits at Sub-V_T

A Survey on Low-Power Techniques with Emerging Technologies

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A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking

Cited by 34 publications

References 2 publications

Power management through DVFS and dynamic body biasing in FD-SOI circuits

Power management through DVFS and dynamic body biasing in FD-SOI circuits

FDSOI Suitability for Asynchronous Circuits at Sub-VT

A Survey on Low-Power Techniques with Emerging Technologies

Contact Info

Product

Resources

About

A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding F_MAX tracking

FDSOI Suitability for Asynchronous Circuits at Sub-V_T