A 4Mb DRAM with cross point trench transistor cell

Shah, A.H.; Wang, Chu-Ping; Womack, R.H.; Gallia, J.; Shichijo, H.; Davis, H.E.; Elahy, M.; Banerjee, Sanjay K.; Pollack, G.; Richardson, W. H.; Bordelon, D.M.; Malhi, S.D.S.; Pilch, C.; Tran, Bao Anh N.; Chatterjee, P.K.

doi:10.1109/isscc.1986.1156951

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Hierarchical Bit-line Architecture1

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1987

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Cited by 17 publications

(2 citation statements)

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“…To solve this dilemma, we re-examine and re-construct the hierarchical bit-line architecture [3]. Fig.…”

Section: Hierarchical Bit-line Architecturementioning

confidence: 99%

A hierarchical bit-line architecture with flexible redundancy and block compare test for 256 Mb DRAM

Asakura

Oishi

Tomishima

et al. 1993

Symposium on VLSI Circuits

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“…To solve this dilemma, we re-examine and re-construct the hierarchical bit-line architecture [3]. Fig.…”

Section: Hierarchical Bit-line Architecturementioning

confidence: 99%

A hierarchical bit-line architecture with flexible redundancy and block compare test for 256 Mb DRAM

Asakura

Oishi

Tomishima

et al. 1993

Symposium on VLSI Circuits

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“…For higher density, main memory applications, the 1-device cell DRAM technology is used [60]. Despite this memory cell change, it is interesting to see in Figure 3 that, empirically, the performance of main memory chips follows the same general performance-size trend as the SRAM chips (see Tables 7 and 8 derived from data in references [61][62][63][64][65][66][67][68][69][70][71][72][73][74]. The data points on Figure 3 represent chips announced at different times using different technologies so that an exact comparison is not possible; nevertheless, the memory access time for IGFET or bipolar technology generally increases (degrades) about 0.6 decades for every decade increase in memory capac- ity.…”

Section: Historical Backgroundmentioning

confidence: 99%

Challenges in advanced semiconductor technology for high-performance and supercomputer applications

Osburn

Reisman

1987

J Supercomput

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This article provides a review of the capabilities, future directions, and technology challenges for semiconductor chips and packages as they apply to high-performance and supercomputer applications. Semiconductor chip technology has resulted in dramatic device density improvements over the last 20 years. Scaling theory predicts that continued improvements will be possible if the technological problems associated with patterning, doping, interconnection, density, yield, and cost can be solved. The issues associated with these challenges are discussed. Finally, the packaging needs to support advanced chip technologies are reviewed.

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Trends in megabit DRAM circuit design

Itoh

1990

IEEE J. Solid-State Circuits

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A 4Mb DRAM with cross point trench transistor cell

Cited by 17 publications

References 3 publications

A hierarchical bit-line architecture with flexible redundancy and block compare test for 256 Mb DRAM

A hierarchical bit-line architecture with flexible redundancy and block compare test for 256 Mb DRAM

Challenges in advanced semiconductor technology for high-performance and supercomputer applications

Trends in megabit DRAM circuit design

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