A 5.0mW 0dBm FSK transmitter for 315/433 MHz ISM applications in 0.25 μm CMOS

Boom, N.; Rens, W.; Crols, Jan

doi:10.1109/esscir.2004.1356652

Cited by 14 publications

(7 citation statements)

References 3 publications

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“…There are three methods of frequency modulation upconversion [19]. To meet the WSN's features, such as simple architecture, low power and low data rate, the best method is direct digital modulation of the Phase-Locked Loop (PLL) [2]: The baseband data are directly fed into the PLL, and then modulated by the PLL. In a low-IF receiver, the frequency synthesizer supplies the receiver with I/Q dualpath Local Oscillating (LO) signals whose phase difference is 90°.…”

Section: Introductionmentioning

confidence: 99%

“…The is contributed;(2) there is only one clock input so that the load of the divider's input port is decreased.In order to compare the transition time of the conventional CML latch and our proposed latch, as show inFig. 9, we set the same size for the transistors divided into a same group:(1)Ma1, Ma2, Mb3 and Mb4; (2) Ma3, Ma4, Ma5, Ma6, Mb1 and Mb2; (3) Ma7, Ma8, Mb5 and Mb6.…”

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confidence: 98%

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A PLL based WSN transmitter and I/Q LO signal generator at 430–435 MHz

Zhao

Guo

Yang

et al. 2011

Analog Integr Circ Sig Process

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A fully integrated Phase-Locked Loop (PLL) based transmitter and I/Q Local Oscillating (LO) signal generator used for half-duplex Wireless Sensor Networks (WSN) transceivers is proposed. Instead of one 430-435 MHz PLL for frequency synthesizing, a 1.72-1.74 GHz PLL is designed together with a 1/4 frequency divider. Then the chip area of the inductors in the Voltage-Controlled Oscillator (VCO) is decreased to about 1/16, and I/Q dual-path LO signals can be obtained without additional power consumption. A Gray-code controlled prescaler is proposed to avoid the glitches and uncertain states, and then the frequency dividing accuracy is improved by 17%. A Gauss Frequency Shift Keying (GFSK) transmitter with a pipeline modulator is proposed, the 1st and 2nd Adjacent Channel Power Ratio (ACPR) are -19.9 and -20.7 dBc, respectively. A mathematical spur model of 1/4 frequency dividers is built here, and then a low-spur 1/4 frequency divider composed of our proposed improved Current Mode Logic (CML) latches is designed. The testing results show that the reference spurs are -61.2 dBc@20 MHz and -57.7 dBc@40 MHz at the output of the PLL, and -70.5 dBc@20 MHz and -66.6 dBc@40 MHz at the output of our 1/4 divider. With 2.6-mW power consumption, our proposed 1/4 frequency divider has a phase-noise contribution of only 0.5 dBc/Hz@500 kHz and 0.2 dBc/Hz@1 MHz.

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Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 98%

A PLL based WSN transmitter and I/Q LO signal generator at 430–435 MHz

Zhao

Guo

Yang

et al. 2011

Analog Integr Circ Sig Process

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“…The open-loop topology needs periodic relocking of the VCO frequency in practice. A PLL-based topology can improve the communication quality because the VCO is always locked by the PLL, 15) but the data rate is limited by the loop bandwidth.…”

Section: Introductionmentioning

confidence: 99%

Low power low phase noise phase locked loop frequency synthesizer with fast locking mode for 2.4 GHz applications

Liu¹,

Feng²,

Liu³

et al. 2014

Jpn. J. Appl. Phys.

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We designed a low power low phase noise phase locked loop (PLL) frequency synthesizer for 2.4 GHz wireless communication applications. Current reusing technique and triple-well NMOS transistors are applied to reduce power consumption and improve phase noise performance of the voltage controlled oscillator (VCO), respectively. The synthesizer has a fast locking mode that uses frequency presetting technique to greatly shorten the locking time. The synthesizer was implemented in 0.18 µm CMOS process. The chip core area is 1.49 mm 2 . Measured results show that the output frequency tuning range is 2.16-2.55 GHz. The phase noise is %124.18 dBc/Hz at 1 MHz from a 2.4 GHz carrier. The power consumption is 4.98 mW and the locking time in fast locking mode is about 4 µs.

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“…Many recent works on transceivers have demonstrated that submicron CMOS process is a good choice to achieve the goals of high integration, low power and low cost [1][2][3][4]. All the building blocks including low noise amplifier (LNA), mixer, frequency synthesizer, power amplifier and other blocks can be integrated together into a single chip.…”

Section: Introductionmentioning

confidence: 99%

A CMOS 434/868 MHz FSK/OOK transmitter with integrated fractional-N PLL

Zhang

Xiaoping

Zhang

et al. 2008

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems

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A 434/868 MHz FSK/OOK transmitter with integrated PLL is reported. Direct digital modulation of a fully integrated ∑-∆ fractional-N PLL frequency synthesizer is used to ensure fine frequency resolution and low phase noise. A wideband VCO together with an Adaptive Frequency Calibration (AFC) is used to cover the desired bands. A differential-to-single output programmable power amplifier is integrated to make the chip low cost and low power. The measurement results show that the phase noise are -76dBc/Hz and -131dBc/Hz at 10-kHz offset and 3-MHz offset with carrier centered at 868 MHz, respectively. The peak output power of the transmitter is 3.5dBm on 50-Ω load and the measured adjacent channel power ratio (ACPR) for 100 kHz channel is less than -50-dBc. The chip is fabricated with 0.35-µm RF CMOS process. The 2-mm 2 transmitter IC including PLL and power amplifier (PA) consumes 87.6mW at 3V voltage supply.I.

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A 5.0mW 0dBm FSK transmitter for 315/433 MHz ISM applications in 0.25 μm CMOS

Cited by 14 publications

References 3 publications

A PLL based WSN transmitter and I/Q LO signal generator at 430–435 MHz

A PLL based WSN transmitter and I/Q LO signal generator at 430–435 MHz

Low power low phase noise phase locked loop frequency synthesizer with fast locking mode for 2.4 GHz applications

A CMOS 434/868 MHz FSK/OOK transmitter with integrated fractional-N PLL

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