A 5.12-GHz LC-based phase-locked loop for silicon pixel readouts of high-energy physics

Li, Xiaoting; Wei, W.; Zhang, Ying; Yan, Xiong-Bo; Jiang, X. S.; Yang, P.

doi:10.1007/s41365-022-01074-2

Cited by 4 publications

(1 citation statement)

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“…The data rate of the full-size HYLITE chip will be 2.5 Gbps. To meet the data output requirement, a data interface is designed, which includes a PLL [8], an 8b10b-encoder, a high-speed serializer [9], and LVDS drivers. For the convenience of wafer tests, we also designed a low-speed serializer.…”

Section: Clock Generation and Data Interfacementioning

confidence: 99%

Optimized design and characterization of HYLITE, a charge-integration readout chip of XFEL

Li,

Wei,

Jiang

et al. 2024

J. Inst.

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HYLITE (High dYnamic range free electron Laser Imaging deTEctor) is a charge-integration pixel readout chip designed for SHINE (Shanghai HIgh repetition rate XFEL aNd Extreme light facility). The target specifications for the full-size HYLITE chip include a pixel matrix of 128 × 128 pixels and a frame rate of 10 kHz. In order to meet these specifications, two small-scale chips, designated HYLITE0.1 and HYLITE0.2, were fabricated and underwent comprehensive testing. Some issues were discovered during tests including the noise performance and the error of output ADU (Analog Digital Units) codes. The HYLITE200S represents the third prototype chip developed to address the above issues. The CDS (Correlated Double Sampling) circuits and glitch-clear clock structures are integrated in pixels. Furthermore, to meet the data output rate requirements of the full-size chip, a high-speed data interface has been designed. Test results show that the signal-to-noise ratio is improved to 9.31 for a 12 keV single photon, and the ADU error is fixed. By integrating a phase-locked loop and a balanced encoding logic, the data interface can work steadily at a speed of 3.125 Gbps.

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Section: Clock Generation and Data Interfacementioning

confidence: 99%