A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors

Abstract

I. INTRODUCTIONRecently, mobile internet devices such as a smart phone or a tablet PC are getting popular. All of them require high speed internet connection and various kinds of applications such as a mobile digital TV, two-dimensional / three-dimensional graphics, a video recording, a high resolution camera and so on [1]. Figure 1 shows a simplified block diagram of a high performance mobile phone system. It consists of four major components such as an RF IC, a baseband processor (BB), an application processor (AP) and a memory chip. A baseband processor is an LSI that processes communication functions such like LTE or W-CDMA. An application processor executes operation system and various applications. In this system, bandwidth between AP and BB, or AP and memory needs to be wide enough to realize many wireless applications. Since battery life is always a concern in a mobile system, a lot of efforts have been made to reduce power consumption of a mobile phone system [1]. In order to improve bandwidth and energy efficiency of inter-chip communication, an inductive-coupling link between a processor chip and a memory chip has been proposed [2,3]. Power consumption in [2] is very small and performance is high enough, however, the occupied area is very large, which is not acceptable from a commercial point of view. For area saving, a burst-mode inductive-coupling link has been proposed [4]. Although the burst-mode link can significantly reduce the area, it consumes more transmission power than [2] because it is based on an asynchronous circuit instead of a synchronous one. For substantial area reduction of an inductor, XY coil technique has been proposed [5]. Orthogonal edges of the coil are drawn by using two different metal layers, which enables EDA tools to utilize an area above/below the coil for automated place-and-route (PnR). Multiple-die stacking using an inductive-coupling link has been proposed for some applications to improve performance and energy efficiency at the same time [3,5]. A purpose of this paper is to propose a through-chip interface that consumes small power with less area especially for a mobile phone system and to discuss design methodology for a practical chip design. Figure 2 shows a part of a proposed mobile phone system and its three-dimensional system integration overview. An application processor (AP), a memory chip and a baseband processor (BB) are tightly connected by inductive-coupling links and stacked in a package. In this proposal, the AP is mounted face-down on a package substrate for rich power delivery. Since power and some signals are connected using wire bonding, the memory chip and the BB are mounted face-up on the AP and the memory chip, respectively. Thickness of each chip is assumed to be 80um, which is a little thicker than [4,7,8], because it can be considered more practical value for mass production. The inductive-coupling link shown on the left in figure 2 is used for AP-memory, AP-BB, BB-memory communication, that is, three-die communication. II. HIGH PERFORMANCE AN...