A 5-bit 1.8 GS/s ADC-based receiver with two-tap low-overhead embedded DFE in 130-nm CMOS

Mahmoudi, Azad; Torkzadeh, Pooya; Dousti, Massoud

doi:10.1016/j.aeue.2018.03.005

Cited by 11 publications

(1 citation statement)

References 30 publications

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“…High-speed ADCs are very important in communication systems such as broadband satellite receivers, cable TV tuners and Software Defined Radio. These applications have a high demand for high sampling rate, high resolution and low power consumption ADCs [1,2,3,4,5,6,7]. TIADC, consisting several parallel sub-channel ADCs which is clocked by sampling clocks with constant phaseshifting, can achieve ultra-high sampling rate [8].…”

Section: Introductionmentioning

confidence: 99%

Calibration of timing mismatch in TIADC based on monotonicity detecting of sampled data

Yin

Sun

Chen

et al. 2020

IEICE Electron. Express

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In this paper, a calibration method aiming at the timing mismatch existing in the TIADC (Time-Interleaved Analog-to-Digital Converter) is proposed. Monotonicity detecting of the sampled data is employed to estimate the mismatch error, in which only additive operation is involved. Besides that, an improved Taylor expansion method is used to compensate the mismatch error. The processes of the estimation and the compensation are designed to constitute an adaptive loop, so that the calibration can be run in real-time. Compared with other approaches, this method consumes less hardware resources and has a good calibration result.

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