A 5 ns store barrier cache with dynamic prediction of load/store conflicts in superscalar processors

Adams, R.D.; Allen, A.J.; Bergkvist, Jörgen; Flaker, R.; Hesson, J.; LeBlanc, J.

doi:10.1109/isscc.1997.585464

Cited by 4 publications

(7 citation statements)

References 8 publications

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“…SMB-specific modifications are in bold. Table (LFST) maps each store PC to the SSN of its most recent dynamic instance 1 . This SMB implementation extends StoreSets by (i) adding to each SSIT entry an additional confidence counter that tracks the stability of the communicating store-load pair and (ii) extending the LFST to track not only the SSN of the most recent dynamic instance of each store PC, but also its input data physical register tag (dtag).…”

Section: Speculative Memory Bypassing (Smb)mentioning

confidence: 99%

“…The load also writes its address into the load queue, to allow its address to be checked by older stores that have yet to execute. 1. As proposed, StoreSets uses the SSIT to map store and load PCs to Store Set IDs, and the LFST to map StoreSet IDs to store queue indices.…”

Section: Speculative Memory Bypassing (Smb)mentioning

confidence: 99%

“…Bypassing prediction, especially the kind performed by NoSQ, is more challenging than other forms of store-load dependence prediction. Dependence-predictors used for load scheduling (i.e., to reduce squashes due to premature load execution) [1,4,8,23,26] must capture only loads that execute out-of-order with respect to older stores on which they depend; they can also represent dependences conservatively because predicting a dependence where none exists only results in a little additional delay. Dependence predictors used for speculative indexed forwarding [19] must capture all in-flight store-load dependences, but can also be conservative.…”

Section: Store-load Bypassing Predictormentioning

confidence: 99%

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NoSQ: Store-Load Communication without a Store Queue

Sha

Martin

Roth

2006

2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06)

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This paper presents NoSQ (short for No Store Queue), a microarchitecture that performs store-load communication without a store queue and without executing stores in the out-of-order engine. NoSQ implements store-load communication using speculative memory bypassing (SMB), the dynamic shortcircuiting of DEF-store-load-USE chains to DEF-USE chains. Whereas previous proposals used SMB as an opportunistic complement to conventional store queue-based forwarding, NoSQ uses SMB as a store queue replacement.NoSQ relies on two supporting mechanisms. The first is an advanced store-load bypassing predictor that for a given dynamic load can predict whether that load will bypass and the identity of the communicating store. The second is an efficient verification mechanism for both bypassed and non-bypassed loads using in-order load re-execution with an SMB-aware store vulnerability window (SVW) filter.The primary benefit of NoSQ is a simple, fast datapath that does not contain store-load forwarding hardware; all loads get their values either from the data cache or from the register file. Experiments show that this simpler design -despite being more speculative -slightly outperforms a conventional store-queue based design on most benchmarks (by 2% on average). Microarchitecture, 2006, MICRO-39, pages 285-296. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. Comments Copyright 2006 IEEE. Reprinted from Proceedings of the 39th Annual IEEE/ACM International Symposium on

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Section: Speculative Memory Bypassing (Smb)mentioning

confidence: 99%

Section: Speculative Memory Bypassing (Smb)mentioning

confidence: 99%

Section: Store-load Bypassing Predictormentioning

confidence: 99%

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NoSQ: Store-Load Communication without a Store Queue

Sha

Martin

Roth

2006

2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06)

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“…The mis-speculation penalty includes the following three components: (1) The work thrown away to recover from the mis-speculation (which in the case of squash invalidation, i.e., invalidating all instructions after the miss-speculated load, may include unrelated computations). (2) The time, if any, required to perform the invalidation. Finally, (3) the opportunity cost associated with not executing some other instructions instead of the mispeculated load and the instructions that used erroneous data [19].…”

Section: Methods For Exploiting Load/store Parallelismmentioning

confidence: 99%

“…In this paper, we study a variety of dynamic, hardware-based methods. In particular, we consider methods that are derived from combinations of the following parameters: (1) whether an address-based scheduler is used, and (2) whether memory dependence speculation [7,11,1,15,19,4,28,9,2,33] is used. In an address-based scheduler, load and store addresses are used to determine memory dependences for guiding load execution.…”

Section: Introductionmentioning

confidence: 99%

Memory dependence speculation tradeoffs in centralized, continuous-window superscalar processors

Moshovos

Sohi

Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550)

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We consider a variety of dynamic, hardware-based methods for exploiting load/store parallelism, including mechanisms that use memory dependence speculation. While previous work has also investigated such methods [19,4], this has been done primarily for split, distributed window processor models. We focus on centralized, continuous-window processor models (the common configuration today). We confirm that exploiting load/ store parallelism can greatly improve performance. Moreover, we show that much of this performance potential can be captured if addresses of the memory locations accessed by both loads and stores can be used to schedule loads. However, using addresses to schedule load execution may not always be an option due to complexity, latency, and cost considerations. For this reason, we also consider configurations that use just memory dependence speculation to guide load execution. We consider a variety of methods and show that speculation/synchronization can be used to effectively exploit virtually all load/store parallelism. We demonstrate that this technique is competitive to or better than the one that uses addresses for scheduling loads. We conclude by discussing why our findings differ, in part, from those reported for split, distributed window processor models.

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Dynamic techniques for load and load-use scheduling

2001

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Modern microprocessors employ dynamic instruction scheduling to select independent instructions for parallel execution. Good scheduling of loads is crucial, since the long latency of some loads makes them likely to degrade performance. A good scheduler attempts to issue loads as early as possible. Scheduling loads is not simple. First, safely resolving a load's input dependences can be done only at execution time, after the load address and all previous store addresses are known. Second, varying load latency makes it difficult to prioritize loads and to efficiently schedule load-dependent instructions. This paper surveys several techniques that optimize load scheduling. Memory disambiguation resolves store-load dependences and enables earlier execution of store-independent loads. Memory renaming and memory bypassing short-circuit memory to streamline the passing of values from stores to loads. Critical path scheduling, pre-execution, and address prediction advance long-latency loads by computing load addresses early, or predicting them. Value prediction short-circuits load execution by predicting the loaded data values. Finally, data speculation and hit-miss prediction help the scheduling of load-dependent instructions.

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A 5 ns store barrier cache with dynamic prediction of load/store conflicts in superscalar processors

Cited by 4 publications

References 8 publications

NoSQ: Store-Load Communication without a Store Queue

NoSQ: Store-Load Communication without a Store Queue

Memory dependence speculation tradeoffs in centralized, continuous-window superscalar processors

Dynamic techniques for load and load-use scheduling

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