A 5 volt high density poly-poly erase flash EPROM cell

Kazerounian, R.; Ali, S.; Ma, Yutao; Eitan, B.

doi:10.1109/iedm.1988.32849

Cited by 16 publications

(2 citation statements)

References 4 publications

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“…However, owing to the lower programming efficiency, devices utilizing the CHEI mechanism for programming usually need an external high-voltage power supply in order to program the cells within a reasonable time [2][3][4]. Basically, this is due to an inherent incompatibility of having a high hot-carrier generation rate and having an oxide field favourable for electron injection [5][6][7]. In practice, both gate and drain voltages are kept high as a compromise.…”

Section: Introductionmentioning

confidence: 99%

Influence of source coupling on the programming and degradation mechanisms of split-gate flash memory devices

Huang

Fang

Yaung

et al. 1999

Semicond. Sci. Technol.

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In this paper, the mechanism of programming operation considering the source-to-floating gate coupling ratio (SCR) in split-gate source-side injected flash memory has been discussed and experimentally demonstrated. The effects of SCR on the programming performance and cycling endurance have also been investigated in detail. The experimental results indicate that the cell with higher SCR possesses a higher programming speed. Under the same programming speed, the higher-SCR cell shows larger cycling endurance compared to lower-SCR cell.

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Section: Introductionmentioning

confidence: 99%

Influence of source coupling on the programming and degradation mechanisms of split-gate flash memory devices

Huang

Fang

Yaung

et al. 1999

Semicond. Sci. Technol.

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“…In these devices the peak of the electric field is near the drain, therefore most of the hot electron are attracted by the drain and only a small fraction of the electrons injected into the gate oxide, which leads to small gate current and low programming efficiency [6], [7]. Enhancing either the vertical electric field in the gate oxide or the lateral electric field in the channel can increase the gate injection current, the former can increase the injection probability, and the latter may enhance the hot electron amount.…”

mentioning

confidence: 99%

High-gate-injection tunneling field effect transistor for flash memory applications

Qin

Cai

et al. 2012

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology

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In this paper, a tunneling filed effect transistor (TFET) based flash memory with high-gate injection efficiency is proposed and experimentally demonstrated. The measured injection efficiency (gate current (I g ) / drain current (I d )) during programming is more than 10 -4 in TFET flash devices which is two orders higher than that of the conventional ones. It is considered that this high injection efficiency is attributed to the strong channel electric field near source region. The results imply that this TFET flash device is promising for low power operation. IntroductionThe tremendous growth in digital consumer applications, such as mobile phones and digital cameras over the past decade has been one of the driving forces for the development of flash memory technology [1]. NOR flash with high reliability and fast random access speed is widely used for code storage applications. With the shrinking size of CMOS devices and market driven, flash memory is moving towards low operating voltage and low power consumption.The Channel-Hot-Electron (CHE) injection mechanism is widely used as a programming technique for NOR flash memory [2], [3]. However, the major drawback is that the gate injection efficiency during programming for NOR flash device is extremely low (usually lower than 10 -6 ), which results in high programming power issue [4]. The fundamental reason for this is the incompatibility between the proper biasing conditions for hot electron generation and the electron injection into the floating gate [5]. In order to increase hot electron generation, a high drain voltage and low gate voltage are required to generate a high lateral channel electric field. However, under this condition, hot electron injection into the floating gate hardly occurs because of the strong repulsive vertical gate oxide field near the drain. On the other hand, a low drain voltage and a high gate voltage are needed to create the high vertical gate oxide field to enhance the injection probability. Therefore, we have to program the conventional flash under a trade-off between the gate and the drain biasing condition. In practice, very high drain and gate voltage are used during programming. This results in low injection efficiency and a large drain current, which leads to low program efficiency and high power consumption.The conventional MOSFET based flash memory use drain-side channel hot electron injection for their programming. In these devices the peak of the electric field is near the drain, therefore most of the hot electron are attracted by the drain and only a small fraction of the electrons injected into the gate oxide, which leads to small gate current and low programming efficiency[6], [7]. Enhancing either the vertical electric field in the gate oxide or the lateral electric field in the channel can increase the gate injection current, the former can increase the injection probability, and the latter may enhance the hot electron amount. Previously, we proposed a kind of new flash cell based on TFET structure with carrier injec...

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Binary and Multilevel Flash Cells

Eitan

Roy²

1999

Flash Memories

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A 5 volt high density poly-poly erase flash EPROM cell

Cited by 16 publications

References 4 publications

Influence of source coupling on the programming and degradation mechanisms of split-gate flash memory devices

Influence of source coupling on the programming and degradation mechanisms of split-gate flash memory devices

High-gate-injection tunneling field effect transistor for flash memory applications

Binary and Multilevel Flash Cells

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