A 50 dB variable gain amplifier using parasitic bipolar transistors in CMOS

Jian, Pan; Abidi,

doi:10.1109/vlsic.1988.1037399

Cited by 19 publications

(11 citation statements)

References 2 publications

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“…This technique achieves relatively small linearity error but with small dynamic range [8,9]. A possible method to generate the desired exponential function is to use parasitic bipolar transistors that are inherent in CMOS processes [10]. Although a parasitic bipolar transistor has an exponential characteristic, it is generally not preferred due to other unfavourable effects such as limited bandwidth, mismatches and strong temperature dependency.…”

Section: Introductionmentioning

confidence: 99%

1.5-V CMOS exponential current generator

Kalenteridis

Vlassis

Siskos

2012

Analog Integr Circ Sig Process

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A new low-voltage CMOS exponential current generator is proposed in this work. MOS transistors in weak-inversion region and a master-slave technique for the temperature compensation were used. The circuit was fabricated with standard CMOS 0.35 lm process using a single supply voltage of 1.5 V. Experimental results validate the theoretical analysis and verify the effectiveness of the proposed structure. A 40 dB range linearly in dB controlled output current with less than 1.5 dB linearity error was achieved. The structure features ±1 and ±3 dB deviations for ±10% supply voltage and 80°C temperature variations, respectively.

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Section: Introductionmentioning

confidence: 99%

1.5-V CMOS exponential current generator

Kalenteridis

Vlassis

Siskos

2012

Analog Integr Circ Sig Process

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“…Circuit designers have come to realize that bipolar transistors inherent in submicron CMOS devices can be used to enhance circuit performance because of their high transconductance and cutoff frequency [2][3][4][5][6][7]. Since this approach requires no modification of the process, it is a cheap, widely applicable and relatively simple alternative.…”

Section: Introductionmentioning

confidence: 99%

1 V, 1.9 GHz mixer using a lateral bipolar transistor in CMOS

Yamaguchi

Salama

2001

Proceedings of the 2001 International Symposium on Low Power Electronics and Design - ISLPED '01

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This paper describes a low power mixer implemented in a standard 0.25 um CMOS process. The mixer uses lateral bipolar transistors in CMOS to form the core of the circuit. No additional processing steps are needed to obtain the BJT when the MOSFET is properly designed. The mixer exhibits 6.5 dB gain, operating at 1.9 GHz from a 1 V supply and a power dissipation of 1.3 mW. Such a mixer is a likely candidate for low power portable wireless applications.

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“…In most cases a more or less elaborate transistor model was used, and the measurements were translated to variations of the model parameters that are hard to extrapolate to regions of operation where that model is no longer valid. Pan and Abidi [4] In this paper, considering that the MOS subthreshold region lacks a satisfactory mathematical model, especially in moderate inversion, we have decided to present results in the most direct manner, as drain current mismatch dis.,. tributions in MOS differential pairs.…”

Section: Introductionmentioning

confidence: 99%