A 50 MIPS (peak) 32/64 b microprocessor

Conrad, R.; Devlin, R.; Dobberpuhl, D.; Gieseke, B.; Heye, R.; Hoeppner, G.; Kowaleski, J.; Ladd, Maureen; Montanaro, J.; Morris, Scott; Stamm, Rebecca L.; Tumblin, H.; Witek, Richard T.

doi:10.1109/isscc.1989.48185

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Architectural Goals1

B 64-b Adder1

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Cited by 4 publications

(3 citation statements)

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“…To run OpenVMS AXP and Unix -and now Microsoft Windows NT™-operating systems we adopted an idea from a previous Digital Equipment Corporation RISC design called PRISM [3]. We placed the underpinnings for interrupt delivery and return, exceptions, context switching, memory management, and error handling in a set of privileged software subroutines called PALcode.…”

Section: Architectural Goalsmentioning

confidence: 99%

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Alpha AXP architecture

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1993

Commun. ACM

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Section: Architectural Goalsmentioning

confidence: 99%

“…AXP architectural ideas came from the PRISM design [3] most notably the PALcode idea. The architecture work was done in the rich environment of dozens and later hundreds of bright, thoughtful, and outspoken professional peers.…”

mentioning

confidence: 99%

Alpha AXP architecture

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1993

Commun. ACM

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“…A difficult circuit problem was the 64-b adder portion of the integer and floating-point ALU's. Unlike a previous high-speed design [3], we set a goal to achieve single-cycle latency in this unit. Fig.…”

Section: B 64-b Addermentioning

confidence: 99%

A 200-MHz 64-b dual-issue CMOS microprocessor

Dobberpuhl

Witek

Allmon

et al. 1992

IEEE J. Solid-State Circuits

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301

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A 400-MIPS/200-MFLOPS (peak) custom 64-b VLSI CPU chip is described. The chip is fabricated in a 0.75pm CMOS technology utilizing three levels of metalization and optimized for 3.3-V operation. The die size is 16.8 mm X 13.9 mm and contains 1.68M transistors. The chip includes separate 8-kilobyte instruction and data caches and a fully pipelined floating-point unit (FPU) that can handle both IEEE and VAX standard floating-point data types. It is designed to execute two instructions per cycle among scoreboarded integer, floatingpoint, address, and branch execution units. Power dissipation is 30 W at 200-MHz operation.

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The Alpha AXP architecture and 21064 processor

McLellan

1993

IEEE Micro

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A 50 MIPS (peak) 32/64 b microprocessor

Cited by 4 publications

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Alpha AXP architecture

Alpha AXP architecture

A 200-MHz 64-b dual-issue CMOS microprocessor

The Alpha AXP architecture and 21064 processor

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