A 500 MHz 16*16 complex multiplier using self-aligned gate heterostructure FET technology

Akinwande,; Mactaggart,; Betz, Johannes; Grider,; Nohava,; Lange,; Tetzlaff, Ronald

doi:10.1109/isscc.1989.48269

Cited by 2 publications

(1 citation statement)

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“…Another complex number multiplier was reported by Akinwande et al [4]. It is a very fast implementation in GaAs heterostructure FET technology and therefore the level of integration is fairly low, resulting in only partial implementation of the multiplier.…”

Section: Im[p] = (A -B)d + B(c + D)mentioning

confidence: 99%

An integrated multiplier for complex numbers

Oklobdzija

Villeger²,

Soulas³

1994

Journal of VLSI Signal Processing

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Abstract. In this article we consider a design of a multiplier for the multiplication of complex numbers. The complex numbers are packed into one 32-bit word. They are represented by two 13-bit parts with the same 6-bit exponent. Multiplication of complex numbers is examined from the perspectives of performance, complexity and silicon area. The design is unique and combines shared Booth encoding for the real and imaginary parts including only one combined modified Wallace tree of 4:2 adders for each part. The regular Wallace tree is compared with the tree of 4:2 adders. This design results in a more compact wiring structure and balanced delays resulting in a faster multiplier circuit. The number of adders used in the multiplier is also reduced. We consider VLSI CMOS technology and the relevant characteristics as they impact the implementation and performance.

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Section: Im[p] = (A -B)d + B(c + D)mentioning

confidence: 99%