A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOS register file

Hwang, Wei; Joshi, Rajiv V.; Henkels, W.H.

doi:10.1109/4.736656

Cited by 41 publications

(17 citation statements)

References 15 publications

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“…Drive current of fixed PMOS keeper (M 1 ) is approximately a linear function of its threshold voltage (1). (1) Note that in this circuit configuration, voltage difference between gate and source of PMOS keeper is a constant value, because this equation is derived under condition specified by definition of UNG. Therefore, assuming V GSP =V NM and V thp = -V th , (1) can be re-written as:…”

Section: Fixed Keepermentioning

confidence: 99%

A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates

Dadgour

Joshi

Banerjee

2006

Proceedings of the 43rd Annual Conference on Design Automation - DAC '06

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Substantial increase in leakage current and threshold voltage fluctuations are making design of robust wide fan-in dynamic gates a challenging task. Traditionally, a PMOS keeper transistor has been employed to compensate for leakage current of pull down (NMOS) network. However, to maintain acceptable noise margin level in sub-100 nm technologies, large PMOS is necessary, which results in substantial contention (during pull down) and severe loss of performance. In this paper, a novel keeper architecture is proposed which is capable of significantly reducing the contention and improving the performance and power consumption. Using circuit simulations, superior characteristics of the proposed keeper is demonstrated in comparison to those of the traditional as well as state-of-the-art keepers. It is shown that for an 8-input OR gate, in presence of 15% V th fluctuations, the proposed architecture can lead to 20%, 15%, and more than 40% reduction in power consumption, mean delay, and standard deviation of delay, respectively, when compared to traditional keeper circuit.

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Section: Fixed Keepermentioning

confidence: 99%

A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates

Dadgour

Joshi

Banerjee

2006

Proceedings of the 43rd Annual Conference on Design Automation - DAC '06

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“…The smaller gate capacitance loading lowers power dissipation for the dynamic circuits. The self-resetting CMOS (SRCMOS) [6,4,5] macros have the performance advantage over the synchronous dominologic due to the absence of any clocked precharge devices in the logic trees. This reduces the loading on the clock distribution of system clock, thereby alleviates clock skew and power problems.…”

Section: Introductionmentioning

confidence: 99%

SOI for asynchronous dynamic circuits

Joshi

Huang

Chuang

2001

Proceedings of the 11th Great Lakes Symposium on VLSI

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A B S T R A C T This paper describes applications of Silicon on Insulator (SOl) to asynchrous dynamic circuits. The application also focuses on some important issues in SOI technology -performance gain, history effect, power reduction and pulsewidth control. These important issues are characterized with the help of selfresetting (SRCMOS) circuits which are used in building Register file macro (8 ports 32 wordline x 64 bitlines) and dynamic latch. The hardware results show that for 0.25#m Partially Depleted (PD) SOI technology shows 20-25% improvement in the performance and the reduction of 7 to 8% in power. Supply voltage, output loading, slew rate, duty cycle, input pulsewidth and temperature the history effect of the macro and is the aggregate of individual gates on the critical path. Based on the hardware it is shown that the performance of both register file and latch improves by 2-3.,5% per 100 C reduction in temperature. The standby power for SOI reduces by 1.5% to 3% per 10 ° C temperature drop down to -300 C. The SOI chip is shown to have more sigrfificant performance improvement at low temperatures compared bulk chip due to the floating body effect which partially offsets the increase in the threshold voltages (Vt). The tow temperature performance gain is attributed to reduction in capacitance (around 7-8%) and rest is due to dynamic threshold voltages. At -300 C the register file is capable of functioning close to 1.02 OHz for read and write operations in a single cycle. The other key finding is the history effect commonly observed in SOl is reduced from 10% to 3°Z0 by lowering the operating temperature from room to -300 C.

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“…Domino circuits are widely used in computer applications such as arithmetic logics, microprocessors [2], [3], multiplexors [4], registers [5], [6], comparators [7] and many other circuits. Domino circuits have better speed and require lesser area as it has single nMOS evaluation network and reduce output load capacitance.…”

Section: Introductionmentioning

confidence: 99%

Low Power Wide Fan-in Control Pulse Operated Domino Multiplexor with Static Switching

Mishra¹,

Modanwal²

2017

IJCA

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In wide fan-in domino multiplexors, significant power losses are introduced due to the high switching activity at both dynamic and output nodes. In this paper a multiplexor is proposed with static switching at both dynamic and output nodes. This technique has a control pulse generator circuit which turns on the pull up transistor conditionally for a short duration only. This technique is advanced than previously existing techniques as it has faster response over other existing techniques but lesser power consumption and lesser area required. Simulation is done using 0.18µm CMOS technology. Power consumption of proposed multiplexor is calculated and the results are compared with existing multiplexors for different loading condition, clock frequency and temperature. For capacitance 100 fF, proposed domino multiplexor circuit reduces power consumption by 81.08%, 17.57% and 25.50% as compared to standard footless domino, SP-Domino and SSPD multiplexors.

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A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOS register file

Cited by 41 publications

References 15 publications

A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates

A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates

SOI for asynchronous dynamic circuits

Low Power Wide Fan-in Control Pulse Operated Domino Multiplexor with Static Switching

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