A 500 MHz time digitizer IC with 15.625 ps resolution

A high-resolution time interpolator based on a delay locked loop and an RC delay line

“…Most of this is spent in the DLL. This represents a significant reduction from 28 W [1], 800 mW [3], and 5.7 W [7] reported in circuits whose performances are summarized in Table II.…”

“…In this simple single -element DLL scheme the resolution is limited by the basic delay cell ( , where is the reference clock period). To improve the time resolution of the single DLL one can try to further divide the delay of the delay cells by performing phase interpolation using an array of phase shifted DLL's [3], [6] or weighted sums of consecutive cell outputs [7]. Alternatively, as proposed here, one can sample the status of the DLL several times with a small time interval between the samples.…”

CMOS time‐to‐digital converters for mixed‐mode signal processing

“…To further improve the resolution to sub‐buffer delay, interpolation between the rising edges of adjacent delay stages can be utilised. The active interpolation approach proposed in [39] (Fig. 4 a ) uses the weighted sum of the differential output voltages of v 1 and v 2 .…”

CMOS Digital Time Amplifiers for High Resolution Timing Measurement

“…In the second approach, the mechanism of conversion relies on sampling the signal of interest into registers which are clocked by closely spaced sampling phases generated from the reference signal, for instance, through the use of a DLL. Closer spacing of the phases can be further achieved through means of interpolation which ultimately result in measured time differences smaller than that of a constituent delay element [1,[6][7][8]. In this technique, the timing of the signal of interest can be deduced to smaller than the spacing of the sampling phases.…”