A 500 MS/s 600 .MU.W 300 .MU.m2 Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35 .MU.m 3.3 v CMOS Process

A 10-bit 50MS/s pipeline ADC based on kickback-rejected comparators improved for small-amplitude inputs

“…Active loads of proposed preamplifiers in [6], [7] and [8] are here replaced by simple resistors, R, to reduce the propagation delay of pre-amplifier stage and speed up the comparison process. Namely, althought the concurrent use of positive nad negative feedback devices in [6], [7] and [8] provides higher gain for pre-amplification, but a greater capacitive loads is also introduced on output nodes which enlarges the time constant of pre-amplifier stage. The propagation delay is more significant when the sampled data in SAH and latched data on comparator should be concurrently captureed for correct subtraction to strictly provide residue for the next amplification.…”

“…Single-Stage kickback-rejected comparators are proposed in [6], [7] and [8] in which a single hardware is scheduled for three operations: reset, pre-amplification and latch. Cascode structure of NMOS devices alongside the muting shared capacitor is utilized to reduce the kickback effect of output latch on analog inputs.…”

“…Cascode structure of NMOS devices alongside the muting shared capacitor is utilized to reduce the kickback effect of output latch on analog inputs. Two, in [6] and [7], and three, in [8], control signals are required for time scheduling in which the amplitude of control signals are also reduced in low-noise comparator of [8]. Although the proposed comparators are optimized for area and power consumption to be repeatedly used in flash structures, but the ability of tracking high-speed inputs are not considered.…”