A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber

Cao, Jun; Zhang, Bo; Singh, Ullas; Cui, Delong; Vasani, Anand; Garg, Anubhav; Zhang, Wei; Kocaman, Namik; Pi, Deyi; Raghavan, Bharath; Pan, Hui; Fujimori, Ichiro; Momtaz, Afshin

doi:10.1109/jssc.2010.2047473

Cited by 63 publications

(11 citation statements)

References 22 publications

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“…The VGA includes three active stages (Fig. 5) and each stage consists of 48 differential pairs connected in parallel with an offset cancellation loop [4,32]. The gain of the stages (A v ) is defined (in first order) by A v % g m R L , where g m is the MOS transconductance and R L is the load resistance.…”

Section: Input Variable Gain Amplifiermentioning

confidence: 99%

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A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques

Reyes

Paulina²,

Sánchez³

et al. 2015

Analog Integr Circ Sig Process

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A 2-GS/s 6-bit time interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is designed and fabricated in a 0.13 lm CMOS process. The architecture uses 8 time-interleaved track-andhold amplifiers (THA) and 16 asynchronous SAR ADCs. The sampling frequency of the TI-ADC can be set from 200 MHz to more than 2 GHz. The chip includes a programmable delay cell array to adjust up to AE25 % the sampling clock phase in each THA, and a multi-channel low voltage differential signaling interface capable of transmitting at full sampling rate (>12 Gb/s), without decimation, off-chip. These blocks make the fabricated ADC an excellent platform to test/evaluate mixed-signal calibration algorithms, which are of great interest for application in high-speed optical systems. Measurements of the fabricated ADC show a peak signal-to-noise-and-distortion ratio of 33.9 dB and a power consumption of 192 mW at 1.2 V.

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Section: Input Variable Gain Amplifiermentioning

confidence: 99%

“…Therefore, a comparator offset calibration is required to avoid intra-slice offset mismatch (i.e., between the two sub-interleaved SAR) 4 .…”

Section: Calibration Of the Comparator Offsetmentioning

confidence: 99%

A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques

Reyes

Paulina²,

Sánchez³

et al. 2015

Analog Integr Circ Sig Process

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show abstract

“…T IME-INTERLEAVED, multi-phase architectures are energy-efficient topologies for implementing high-speed analog-to-digital converters (ADCs) and multi-phase serial links [1], [2]. By using multiple phases, lower frequency clocks can relax the front-end track/hold speed, therefore relaxing the bandwidth requirement for the sub-ADCs.…”

Section: Sub-2-ps Static Phase Error Calibration Technique Incorporamentioning

confidence: 99%

Sub-2-ps, Static Phase Error Calibration Technique Incorporating Measurement Uncertainty Cancellation for Multi-Gigahertz Time-Interleaved T/H Circuits

Xia

Wang

Beattie

et al. 2012

IEEE Trans. Circuits Syst. I

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A foreground digital calibration method is presented that calibrates the timing offsets between the multiple T/H (track/hold) circuits of time-interleaved analog-to-digital converters and multi-phase serial links. Two quantizer-based phase detectors sample the outputs of adjacent track/hold circuits, detecting any phase offsets arising from process mismatches in both the timing verniers and the T/H switches, and store the resulting digital decisions in histogram counters. Measurement inaccuracies resulting from quantizer offset are averaged away statistically by a round-robin rotation of the dual samplers, compensating for comparator imprecision. Built in a 90-nm CMOS process, the proposed calibration technique, after three iterations of both the phase measurement and subsequent timing vernier adjustment, reduces the static phase offset of each channel to less than 0 5 ps in an 8-channel, 8 GS/s time-interleaved system. Further measurements using a T/H circuit as a down-conversionmixer confirm a residual phase error of less than 2 ps.

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“…But the complexity involved in such techniques is resulting in a trend towards fully ADCbased transceivers that would move complex equalization and clock recovery blocks into the digital domain. Results have shown that feed-forward digital clock and data recovery is possible up to 10 Gb/s [1].…”

Section: Introductionmentioning

confidence: 99%

A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC

Bichan

Dunwell

Wang

et al. 2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper analyzes the impact of clock skew between comparators in a flash ADC, showing that the SNDR penalty introduced by this effect can become significant at high frequencies. To address this issue, a passive resonant clock network is proposed to distribute the clock to the comparators in a flash ADC. The inductive termination of this network serves to resonate out the parasitic and input capacitances of the ADC, allowing for a 2.5-GHz clock signal to be conveyed to a load of 256 comparators while consuming less power than traditional clock networks due to the reduced number of active clock buffers required. This clock network produces little timing skew at the resonant frequency, thereby obviating the need for a track-andhold amplifier, which further reduces the power requirements of the ADC. This clock network was implemented in a 5-bit flash ADC designed in 65 nm CMOS, with a measured SNDR of 26 dB.

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A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber

Cited by 63 publications

References 22 publications

A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques

A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques

Sub-2-ps, Static Phase Error Calibration Technique Incorporating Measurement Uncertainty Cancellation for Multi-Gigahertz Time-Interleaved T/H Circuits

A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC

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