A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS

Romanovsky, S.; Katoch, A.; Achyuthan, A.; O'Connell, C.; Natarajan, S.; Huang, Chien-Yao; Chen, Wu; Wang, Min-Jer; Wang, C.J.; Chen, P.; Hsieh, R. L.

doi:10.1109/isscc.2008.4523161

Cited by 21 publications

(6 citation statements)

References 2 publications

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“…area, access latency and leakage) of the modeled memories. In order to validate CACTI results, we have modeled a real eDRAM macro [16] and found that they are very similar to the actual physical parameters. Thus, we used physical parameters provided by CACTI to evaluate static power consumed and the area required by the memory structures.…”

Section: Experimental Methodologymentioning

confidence: 98%

Implementing a hybrid SRAM / eDRAM NUCA architecture

Lira

Molina

Brooks

et al. 2011

2011 18th International Conference on High Performance Computing

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Abstract-Advances in technology allowed for integrating DRAM-like structures into the chip, called embedded DRAM (eDRAM). This technology has already been successfully implemented in some GPUs and other graphic-intensive SoC, like game consoles. The most recent processor from IBM R , POWER7, is the first general-purpose processor that integrates an eDRAM module on the chip. In this paper, we propose a hybrid cache architecture that exploits the main features of both memory technologies, speed of SRAM and high density of eDRAM. We demonstrate, that due to the high locality found in emerging applications, a high percentage of data that enters to the on-chip last-level cache are not accessed again before they are evicted. Based on that observation, we propose a placement scheme where re-accessed data blocks are stored in fast, but costly in terms of area and power, SRAM banks, while eDRAM banks store data blocks that just arrive to the NUCA cache or were demoted from a SRAM bank. We show that a well-balanced SRAM / eDRAM NUCA cache can achieve similar performance results than using a NUCA cache composed of only SRAM banks, but reduces area by 15% and power consumed by 10%. Furthermore, we also explore several alternatives to exploit the area reduction we gain by using the hybrid architecture, resulting in an overall performance improvement of 4%.

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Section: Experimental Methodologymentioning

confidence: 98%

Implementing a hybrid SRAM / eDRAM NUCA architecture

Lira

Molina

Brooks

et al. 2011

2011 18th International Conference on High Performance Computing

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show abstract

“…Equations (7) and (8) are used to obtain the instantaneous angles (θ, ϕ) of the magnetization vector at any time with any given voltage across the STR. With the instantaneous value of θ, the MTJ resistance (also called magnetoresistance) in our electrical model can be calculated using (1).…”

Section: Stress Anisotropy In the Nm Due To Magnetostrictionmentioning

confidence: 99%

Straintronics-Based Random Access Memory as Universal Data Storage Devices

Barangi

Mazumder

2015

IEEE Trans. Magn.

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Nanomagnetic and spin-based memories are distinguished for their high data endurance in comparison with their charge-based peers. However, they have drawbacks, such as high write energy and poor scalability due to high write current. In this paper, we apply the straintronics principle that seeks the combination of piezoelectricity and inverse magnetostriction (Villari effect), to design a proof-of-principle 2 Kb nonvolatile magnetic memory in 65 nm CMOS technology. Our simulation results show read-access and write-cycle energies as low as 49 and 143 fJ/b, respectively. At a nominal supply level of 1 V, reading can be performed as fast as 562 MHz. Write error rates <10 −7 and 10 −15 can be obtained at 10 and 5 MHz, respectively. In addition to nonvolatility, ultralow energy per operation, and high performance, our STRs memory has a high storage density with a cell size as small as 0.2 µm 2 .

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“…Need for larger memory and corresponding logic circuitry keeps growing up with technology scaling as well. There have been abundant and excellent researches especially on embedded memory systems exclusively dedicated to data storage [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17]. The IBM research team demonstrated a paradigm-shifting approach of computational memory by using 1M phase change memory devices exploiting crystallization dynamics organized to perform massive data processing on temporally correlated data between event-based data streams [18].…”

Section: Introductionmentioning

confidence: 99%

A 0.94 μW 611 KHz In-Situ Logic Operation in Embedded DRAM Memory Arrays in 90 nm CMOS

Hwang

Kwon

2019

Electronics

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Conventional computers based on the Von Neumann architecture conduct computation with repeated data movements between their separate processing and memory units, where each movement takes time and energy. Unlike this approach, we experimentally study memory that can perform computation as well as store data within a generic memory array in a non-Von Neumann architecture way. Memory array can innately perform NOR operation that is functionally complete and thus realize any Boolean functions like inversion (NOT), disjunction (OR) and conjunction (AND) operations. With theoretical exploration of memory array performing Boolean computation along with storing data, we demonstrate another potential of memory array with a test chip fabricated in a 90 nm logic process. Measurement results confirm valid in-situ memory logic operations in a 32-kbit memory system that successfully operates down to 135 mV consuming 130 nW at 750 Hz, reducing power and data traffic between the units by five orders of magnitude at the sacrifice of performance.

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A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS

Cited by 21 publications

References 2 publications

Implementing a hybrid SRAM / eDRAM NUCA architecture

Implementing a hybrid SRAM / eDRAM NUCA architecture

Straintronics-Based Random Access Memory as Universal Data Storage Devices

A 0.94 μW 611 KHz In-Situ Logic Operation in Embedded DRAM Memory Arrays in 90 nm CMOS

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