A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier

Barth, J.; Reohr, W.; Parries, P.; Fredeman, Gregory; Golz, John; Schuster, S.E.; Matick, Richard E.; Hunter, Hillery C.; Tanner, Charles C.; Harig, J.; Kim, H.; Khan, Babar A.; Griesemer, J.; Havreluk, R.; Yanagisawa, K.; Kirihata, T.; Iyer, Subramanian S.

doi:10.1109/isscc.2007.373506

Cited by 25 publications

(9 citation statements)

References 8 publications

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“…Barth et al [3] have reported retention times of 40 µs as well. Therefore, it is clear that, overall, eDRAMs are refreshed at a very pessimistic rate.…”

Section: Retention Time Variationmentioning

confidence: 94%

“…However, in practice, eDRAM cells are refreshed with a period of the order of a few tens of microseconds. For example, Barth et al [3] report a time of 40 µs. This is because manufacturing process variations result in a distribution of retention times and, to attain a high yield, manufacturers choose the retention time for the entire memory module to be the one of the leakiest cells.…”

Section: Edram Cell Retention Timementioning

confidence: 99%

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Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules

Agrawal

Ansari

Torrellas

2014

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)

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EDRAM cells require periodic refresh, which ends up consuming substantial energy for large last-level caches. In practice, it is well known that different eDRAM cells can exhibit very different charge-retention properties. Unfortunately, current systems pessimistically assume worst-case retention times, and end up refreshing all the cells at a conservatively-high rate. In this paper, we propose an alternative approach. We use known facts about the factors that determine the retention properties of cells to build a new model of eDRAM retention times. The model is called Mosaic. The model shows that the retention times of cells in large eDRAM modules exhibit spatial correlation. Therefore, we logically divide the eDRAM module into regions or tiles, profile the retention properties of each tile, and program their refresh requirements in small counters in the cache controller. With this architecture, also called Mosaic, we refresh each tile at a different rate. The result is a 20x reduction in the number of refreshes in large eDRAM modules -practically eliminating refresh as a source of energy consumption.

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“…Barth et al [3] have reported retention times of 40 µs as well. Therefore, it is clear that, overall, eDRAMs are refreshed at a very pessimistic rate.…”

Section: Retention Time Variationmentioning

confidence: 94%

Section: Edram Cell Retention Timementioning

confidence: 99%

Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules

Agrawal

Ansari

Torrellas

2014

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)

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“…Volatile memory technologies, such as Embedded DRAM (eDRAM) [5] and Hybrid Memory Cube (HMC) [6] address the performance and energy inefficiency of DDR DRAM technology. eDRAM is DRAM embedded on the processor chip.…”

Section: A Characteristics Of Future Memory Technologiesmentioning

confidence: 99%

“…Volatile memories are one such technology, which have retention times comparable to DRAM (order of nanosecond) and also need frequent refresh, similar to DRAM. They are based on DRAM cell technology but improve on the architecture and the interface to deliver higher performance and energy efficiency than DRAM [5,6]. Also emerging as a technology solution are non-volatile memories (NVM), which have much longer retention times than DRAM (order of years), are based on new cell technologies and offer improvements mostly towards capacity [7].…”

Section: Introductionmentioning

confidence: 99%

Evaluation of emerging memory technologies for HPC, data intensive applications

Suresh

Cicotti

Carrington

2014

2014 IEEE International Conference on Cluster Computing (CLUSTER)

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DRAM technology has several shortcomings in terms of performance, energy efficiency and scaling. Several emerging memory technologies have the potential to compensate for the limitations of DRAM when replacing or complementing DRAM in the memory sub-system. In this paper, we evaluate the impact of emerging technologies on HPC and data-intensive workloads modeling a 5-level hybrid memory hierarchy design. Our results show that 1) an additional level of faster DRAM technology (i.e. EDRAM or HMC) interposed between the last level cache and DRAM can improve performance and energy efficiency, 2) a non-volatile main memory (i.e. PCM, STTRAM, or FeRAM) with a small DRAM acting as a cache can reduce the cost and energy consumption at large capacities, and 3) a combination of the two approaches, which essentially replaces the traditional DRAM with a small EDRAM or HMC cache between the last level cache and the non-volatile memory, can grant capacity and improved performance and energy efficiency. We also explore a hybrid DRAM-NVM design with a partitioned address space and find that this approach is marginally beneficial compared to the simpler 5-level design. Finally, we generalize our analysis and show the impact of emerging technologies for a range of latency and energy parameters.

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“…Embedded DRAM (eDRAM) has been proposed for large memory arrays. eDRAM clock speed and access time have been improved to match the SRAM typical behavior [6]. However, using eDRAM requires to integrate more dense capacitors in the logic technology process, and thus needs costly additional process steps.…”

mentioning

confidence: 99%

A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context.

Vignon¹,

Cosemans²,

Dehaene³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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This paper presents a DRAM architecture that improves the DRAM performance/power trade-off to increase their usability on low power chip design using 3D interconnect technology. The use of a finer matrix subdivision and buffering the bitline signal at the localblock level allows to reduce both the energy per access and the access time. The obtained performances match those of a typical low power SRAM, while achieving a significant area and static power reduction compared to these memories.The 128 kb memory architecture proposed here achieves an access time of 1.3 ns for a dynamic energy of less than 0.2 pJ per bit. A localized refresh mechanism allows gaining a factor of 10 in static power consumption associated with the cell, and a factor of 2 in area, when compared with an equivalent SRAM. I. CONTEXTAs feature size reduces, on-chip memory design is becoming more and more challenging. Reducing the typical dimensions and the supply voltage for SRAM memories degrades the cell stability [1]. The stability is degraded further by intradie variations which lead in addition to increased average power consumption. Several solutions have been investigated to reduce this issue, from changing the cell topology [2] [3] [4] to modifying the peripheral architecture [5]. However, these solutions increase the memory area and thus compromise scaling. Embedded DRAM (eDRAM) has been proposed for large memory arrays. eDRAM clock speed and access time have been improved to match the SRAM typical behavior [6]. However, using eDRAM requires to integrate more dense capacitors in the logic technology process, and thus needs costly additional process steps.3D interconnect enables the use of heterogeneous technologies on the same chip. 3D vias are typically smaller and have less parasitic capacitance than off-chip connections [7]. In addition, they can be spread across the chip. This reduces the routing energy, and increases the number of available connections between two stacked dies.These advantages allow to provide a better bandwidthenergy trade off for the routing between two stacked dies than between two packaged dies. A possible application of 3D interconnect is to separate the logic core of a system from the Fig. 1. Global architecture -WL/BL subdivision Local_Address Block_address Global_SA Mux GBL data_out LWL receiver Local SA 32x32 cells x16 x16 GWL memory it requires. Such systems have already been studied in [8] [9], with stacks of an SRAM matrix on top of a logic layer. It is also possible to stack DRAM on top of a logic layer.This solution offers numerous other advantages compared to packaged DRAM, including simpler inputs/outputs protocol, and can solve the terminations and clock synchronisation issues by using shorter connections. This allows using conventional DRAM instead of SRAM or embedded DRAM for the largest memories in SOC, bringing a higher density compared to SRAM, without the need to integrate dedicated capacitors in the logic process, as for eDRAM.However, traditional DRAM is outperformed by SRAM in several dom...

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A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier

Cited by 25 publications

References 8 publications

Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules

Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules

Evaluation of emerging memory technologies for HPC, data intensive applications

A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context.

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