A 512 Kbit low-voltage NV-SRAM with the size of a conventional SRAM

Miwa, T.; Yamada, Jun−ichi; Koike, Hideaki; Nakura, Toru; Kobayashi, Toshio; Kasai, Naruhiko; Toyoshima, Hisashi

doi:10.1109/vlsic.2001.934217

Cited by 12 publications

(4 citation statements)

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“…13,14) There have been reported few works that aim for realizing a large signal memory cell using STT-MTJ to be used as a component of LSIs. [15][16][17] In this paper, a memory cell that consists of four MOSFETs and two STT-MTJs is firstly proposed. The data are held in a complementary form, making the read data enlarged for a fast and easy access without reference cells.…”

Section: Introductionmentioning

confidence: 99%

High-Density and Low-Power Nonvolatile Static Random Access Memory Using Spin-Transfer-Torque Magnetic Tunnel Junction

Ohsawa

Iga

Ikeda

et al. 2012

Jpn. J. Appl. Phys.

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A novel nonvolatile static random access memory cell is proposed that consists of four transistors and two spin-transfer-torque magnetic tunnel junctions (STT-MTJs). In the case of the NFET driver cell, the free layers of the magnetic tunnel junctions are connected to the transistors' sources and drains to make the cell read-disturb free. The static power is totally eliminated as the power line is shut down during data hold. The static noise margin of the cell is calculated based on the experimental data on MTJ switching that is enhanced from the resistive load SRAM cell due to the MTJ's switching operation. The cell size is estimated to become smaller than the 6-transistor SRAM cell when it is designed at 45 nm node and beyond owing to the MTJ's area shrink as well as the thinning of its tunnel dielectrics (MgO).

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Section: Introductionmentioning

confidence: 99%

High-Density and Low-Power Nonvolatile Static Random Access Memory Using Spin-Transfer-Torque Magnetic Tunnel Junction

Ohsawa

Iga

Ikeda

et al. 2012

Jpn. J. Appl. Phys.

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“…Figure 18 shows the structure of the multiplexer. The multiplexer consists of a conventional multiplexer and an FC-based nonvolatile SRAM [13]. In order to reduce the area overhead of the multiplexers, each of the multiplexers is shared among the MC-switches on the same column of each part.…”

Section: Area-efficient Switch Block Architecture and Evaluationmentioning

confidence: 99%

A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals

Ishihara

Idobata

Hariyama

et al. 2010

IEICE Trans. Inf. & Syst.

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SUMMARYDynamically Programmable Gate Arrays (DPGAs) provide more area-efficient implementations than conventional Field Programmable Gate Arrays (FPGAs). One of typical DPGA architectures is multi-context architecture. An DPGA based on multi-context architecture is Multi-Context FPGA (MC-FPGA) which achieves fast switching between contexts. The problem of the conventional SRAM-based MC-FPGA is its large area and standby power dissipation because of the large number of configuration memory bits. Moreover, since SRAM is volatile, the SRAM-based multi-context FPGA is difficult to implement power-gating for standby power reduction. This paper presents an area-efficient and nonvolatile multi-context switch block architecture for MC-FPGAs based on a ferroelectric-capacitor functional pass-gate which merges a multiplevalued threshold function and a nonvolatile multiple-valued storage. The test chip for four contexts is fabricated in a 0.35 µm-CMOS/0.60 µm-ferroelectric-capacitor process. The transistor count of the proposed multicontext switch block is reduced to 63% in comparison with that of the SRAM-based one. key words: dynamically programmable gate array, multi-context switch, logic-in-memory circuit, multiple-valued threshold logic, nonvolatile storage, non-destructive operation

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“…The transitions for getting into and out of the shutdown period have been completed within 2.5 and 7.5 ns, respectively, at 1.8 V. These transitions are ten times faster than those of the NVFFs using Pb 1Àx Zr x TiO 3 (PZT) capacitors reported thus far. 8,9) It is considered that the fast transitions are attributed to the low dielectric permittivity of SBT (" r $ 300) compared with that of PZT (" r $ 700). Accordingly, the NVFFs with SBT capacitors can effectively reduce the standby power of power-managed systems with frequent transitions.…”

Section: Low-power Consumptionmentioning

confidence: 99%

Overview and Future Challenge of Ferroelectric Random Access Memory Technologies

Kato

Kaneko

Tanaka

et al. 2007

jjap

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We have developed a low-temperature formation technique for ferroelectrics (<500 °C), which is crucial for the ferroelectric random access memory (FeRAM) to be embedded in a leading-edge complementary metal oxide semiconductor (CMOS). A 53-nm-thick Bi4Ti3O12 film was successfully formed by metalorganic chemical vapor deposition at 450 °C and subsequent annealing at 500 °C. It was found that perovskite grains preferentially orient along the (110) and (111) directions and that the fabricated Bi4Ti3O12 capacitors show a remnant polarization (2Pr) of as large as 25.7 µC/cm2. In addition, we have adopted a nondestructive readout operation (NDRO) technique to extend read cycle endurance, in which the switched polarization at reading is automatically rewritten by readout voltage removal. We have demonstrated stable readout characteristics at more than 1011 cycles for 0.18 µm NDRO FeRAMs.

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A 512 Kbit low-voltage NV-SRAM with the size of a conventional SRAM

Cited by 12 publications

References 1 publication

High-Density and Low-Power Nonvolatile Static Random Access Memory Using Spin-Transfer-Torque Magnetic Tunnel Junction

High-Density and Low-Power Nonvolatile Static Random Access Memory Using Spin-Transfer-Torque Magnetic Tunnel Junction

A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals

Overview and Future Challenge of Ferroelectric Random Access Memory Technologies

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