A 52 dB-SFDR 166 MHz sinusoidal signal generator for mixed-signal BIST applications in 28 nm FDSOI technology

Malloug, Hani; Barragán, Manuel J.; Mir, Salvador

doi:10.1109/ets.2019.8791532

Cited by 8 publications

(7 citation statements)

References 8 publications

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“…Harmonic cancellation techniques have been widely employed in the last few years for the implementation of on-chip sinusoidal signal generators due to the reduced complexity and enhanced performance that can be achieved compared to other architectures [1]- [7], [9]. Although each particular implementation may vary, these signal generators share the same operating principle.…”

Section: Previous Workmentioning

confidence: 99%

“…The works in [3]- [7], [9], on the other hand, rely on digital circuitry and employ time-shifted versions of a digital square wave as the base signal for the harmonic cancellation. The generation of these time-shifted square-waves can be easily performed in the digital domain, while the scaling and combination of the different signals is carried out using some Digitalto-Analog architecture.…”

Section: Previous Workmentioning

confidence: 99%

“…The works in [5], [7], [9] target higher generated frequencies in the range of hundreds of MHz. Thus, [5] employs a ring oscillator for generating time-shifted square-wave signals while a weighted resistor summing network is used to scale and combine these time-shifted signals in the analog domain.…”

Section: Previous Workmentioning

confidence: 99%

“…Grenoble Alpes been repeatedly identified as one of the main blocking points for moving many AMS-RF tests to a practical BIST scheme. In this sense, recently proposed on-chip sinusoidal signal generators make use of harmonic cancellation techniques in order to reduce circuit complexity -in some cases relying mostly on digital circuitry-while providing a highly-linear output signal [1]- [9]. Harmonic cancellation techniques are based on combining a set of delayed and weighted versions of a given periodic signal in order to cancel out the most significant undesired harmonic components in the original periodic signal [10].…”

Section: Introductionmentioning

confidence: 99%

“…Harmonic cancellation techniques are based on combining a set of delayed and weighted versions of a given periodic signal in order to cancel out the most significant undesired harmonic components in the original periodic signal [10]. The technique can be successfully applied using digital square waves as the original periodic signal [3]- [9]. This makes this technique very suitable for a digitalfriendly integration of AMS-RF test techniques.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Analysis and mitigation of timing inaccuracies in high-frequency on-chip sinusoidal signal generators based on harmonic cancellation

Mamgain

Barragán

Mir

2021

2021 IEEE European Test Symposium (ETS)

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On-chip sinusoidal signal generators are a key element for enabling a wide variety of DfT and BIST applications for AMS-RF integrated circuits. Harmonic cancellation techniques have been recently proposed for the efficient implementation of high-quality embedded sinusoidal signal generators. However, harmonic cancellation techniques, based on phase-shifting and combining a set of periodic signals, rely on precise and accurate phase-shift control which makes them very sensitive to timing issues due to mismatch, noise, etc. Timing issues can severely limit the performance of these generators especially in high-frequency applications where precise timing becomes challenging. In this paper, we analyze the effects of timing inaccuracies on highspeed harmonic cancellation generators and we propose circuit techniques for mitigating them. Electrical simulation results on a 1.45 GHz sinusoidal signal generator implemented in ST 28 nm FDSOI technology are provided to validate our proposals.

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Section: Previous Workmentioning

confidence: 99%

Section: Previous Workmentioning

confidence: 99%

Section: Previous Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Analysis and mitigation of timing inaccuracies in high-frequency on-chip sinusoidal signal generators based on harmonic cancellation

Mamgain

Barragán

Mir

2021

2021 IEEE European Test Symposium (ETS)

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On-chip calibration for high-speed harmonic cancellation-based sinusoidal signal generators

Mamgain

Mir

Tripathi

et al. 2022

2022 IEEE 31st Asian Test Symposium (ATS)

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Harmonic cancellation techniques have been exploited for the on-chip generation of high-linearity sinusoidal test stimuli. The sinusoidal signal is generated by combining timeshifted and scaled versions of a periodical signal, in such a way that by properly choosing the time-shifts and weights, the lower order harmonics are canceled. However, process variations and mismatch can degrade the effectiveness of the harmonic cancellation, since precise time-shifts and scale ratios are required. In this regard, timing inaccuracies are especially harmful in the implementation of high-speed harmonic cancelling generators. In this paper, we propose an on-chip calibration architecture that can correct the phase-shift and duty-cycle of the signals with the help of a negative feedback loop. Electrical simulation results at transistor level show the feasibility of the calibration technique for a sinusoidal signal generator implemented in ST 28 nm FD-SOI technology. Obtained results show a Total Harmonic Distortion (THD) better than −60 dB after calibration in an output frequency range from 200 MHz to 4 GHz.

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High-coverage analog IP block test generation methodology using low-cost signal generation and output response analysis

Gomez

Xama

Coyette

et al. 2023

2023 IEEE European Test Symposium (ETS)

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A 52 dB-SFDR 166 MHz sinusoidal signal generator for mixed-signal BIST applications in 28 nm FDSOI technology

Cited by 8 publications

References 8 publications

Analysis and mitigation of timing inaccuracies in high-frequency on-chip sinusoidal signal generators based on harmonic cancellation

Analysis and mitigation of timing inaccuracies in high-frequency on-chip sinusoidal signal generators based on harmonic cancellation

On-chip calibration for high-speed harmonic cancellation-based sinusoidal signal generators

High-coverage analog IP block test generation methodology using low-cost signal generation and output response analysis

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