A 52 GHz Phased-Array Receiver Front-End in 90 nm Digital CMOS

Scheir, Karen; Bronckers, Stephane; Borremans, Jonathan; Wambacq, Piet; Rolain, Yves

doi:10.1109/jssc.2008.2004861

Cited by 92 publications

(30 citation statements)

References 18 publications

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“…To ease installation and maintenance, beam steering [1] would thus be beneficial. Beam steering can be implemented in the RF path, in the LO path, or in the baseband [2], where implementation in the digital domain is the most flexible solution but also has the drawback that separate ADCs and DACs are required for each receive and transmit path. The architecture of the LO signal generation is also important to consider.…”

Section: Introductionmentioning

confidence: 99%

“…The architecture of the LO signal generation is also important to consider. Using a single quadrature LO generation and distributing its four output signals across the chip to each transceiver is a less attractive solution [2,3]. At mm-wave frequencies the power consumption of the LO buffers required for signal distribution would be very large in comparison with other transceiver parts.…”

Section: Introductionmentioning

confidence: 99%

“…At mm-wave frequencies the power consumption of the LO buffers required for signal distribution would be very large in comparison with other transceiver parts. Long routing will also result in phase and amplitude mismatch of the LO signals [2][3][4]. Since spectral efficiency of the radio link is important, next generation E-band links will use e.g.…”

Section: Introductionmentioning

confidence: 99%

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A 28 GHz SiGe PLL for an 81–86 GHz E-band beam steering transmitter and an I/Q phase imbalance detection and compensation circuit

Tired

Sjöland

Sandrup

et al. 2015

Analog Integr Circ Sig Process

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This paper presents two circuits, a complete 1.5 V 28 GHz SiGe beam steering PLL and a standalone 28 GHz QVCO with I/Q phase imbalance detection and compensation. The circuits were designed in a SiGe process with f T = 200 GHz. The PLL is intended to be used for beam steering in an 81-86 GHz E-band transmitter. Phase control is implemented by DC current injection at the output of a Gilbert architecture phase detector showing a simulated phase control sensitivity of 1.2°/lA over a range close to 180°. The simulations use layout parasitics for the QVCO, frequency divider, and phase detector, and an electromagnetic model for the QVCO inductors. The divider is implemented with four cascaded divide-by-two current-mode-logic blocks for a reference frequency of 1.75 GHz. For closed loop simulations of PLL noise and stability, the QVCO is represented with a behavior model with added phase noise. This simulation technique enabled faster simulation time of the PLL. The PLL in band phase noise at 1 MHz offset equals -115 dBc/Hz. Excluding output buffers, the entire PLL consumes 52 mW plus a minimum 7 mW from a variable high voltage supply required to extend the PLL locking range. The measured phase noise of the standalone QVCO equals -100 dBc/Hz at 1 MHz offset. Since E-band radio links utilize higher order QAM modulation, the bit-error rate is sensitive to I/Q phase error. In the measured standalone QVCO with I/Q phase imbalance detection and compensation, the error is detected in two cross coupled active mixers that have an output DC level proportional to the phase error. The error can then be eliminated adjusting the bias of four varactors connected to the QVCO outputs. The current consumption of the chip equals 14 mA from a 1.5 V supply and 57 mA from a 2.5 V supply dedicated to the detector and 28 GHz output measurement buffers.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A 28 GHz SiGe PLL for an 81–86 GHz E-band beam steering transmitter and an I/Q phase imbalance detection and compensation circuit

Tired

Sjöland

Sandrup

et al. 2015

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

show abstract

“…Local Oscillator beamforming architectures [10,11] separate the signal path from the phase control circuit, and thus allows more freedom in designing the transceiver than RF phase shifting. A benefit of the LO beamforming architecture is also that each signal path exhibits very low, if any, variation in important parameters like gain, matching, noise, linearity, and power consumption versus phase shift.…”

Section: Introductionmentioning

confidence: 99%

A PLL based 12 GHz LO generator with digital phase control in 90 nm CMOS

Axholt

Sjöland

2011

Analog Integr Circ Sig Process

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A 12 GHz PLL with digital output phase control has been implemented in a 90 nm CMOS process. It is intended for LO signal generation in integrated phased array transceivers. Locally placed PLLs eliminate the need of long high frequency LO routing to each transceiver in a phased array circuit. Routing losses are thereby reduced and the design of integrated phased array transceivers becomes more modular. A chip was manufactured, featuring two separate fully integrated PLLs operating at 12 GHz, with a common 1.5 GHz reference. The chip, including pads, measures 1050 9 700 lm 2 . Each PLL consumes 15 mA from a 1.2 V supply, with a typical measured phase noise of -110 dBc/Hz at 1 MHz offset. The phase control range exceeds 360°.

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“…Table 1 compares our receiver's performance with the state-of-the-art [4][5][6]. Our work exhibits the highest conversion gain, lowest NF, area, and DC power consumption.…”

mentioning

confidence: 99%

65 nm CMOS receiver with 4.2 dB NF and 66 dB gain for 60 GHz applications

Wang

Liu

et al. 2011

Electron. Lett.

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A direct conversion receiver for 60 GHz applications is fabricated in 65 nm CMOS. It consists of three low-noise amplifier gain stages, an RF mixer, a lowpass filter and a three-stage programmable gain amplifier. An overall minimum noise figure (NF) of 4.2 dB and maximum gain of 66 dB is achieved by the receiver occupying a core area of 0.26 mm 2 while drawing 36 mA of current from a 1 V supply.Introduction: The 7 GHz of unlicensed band around 60 GHz has spurred intense research activities relating to low-cost, low-power and highly integrated circuits for applications in ultra-high data-rate wireless communications. Recent studies have shown deep-scaled CMOS to be a promising technology for achieving a cost-effective monolithic solution [1]. To enable high-order modulation schemes (i.e. 16QAM and above), the receiver noise figure (NF) must be sufficiently low. However, the low NF should not come at the expense of excessive power consumption for portable applications. Consequently, a compact, low-noise, low-power consumption receiver design is highly desirable.Taking account of the above considerations, we have designed and implemented a low-noise, low-power receiver in 65 nm general purpose (GP) CMOS. As shown in Fig. 1, it is a direct-conversion receiver with a low-noise amplifier (LNA) tuned to 60 GHz followed by a mixer that down converts a RF signal to baseband with an external local oscillator (LO). The lowpass filter (LPF) and programmable gain amplifier (PGA) follow to complete the receiver chain. The prototype receiver achieves a maximum gain of 66 dB and a minimum NF of 4.2 dB with a compact area of 0.256 mm 2 , while dissipating 36 mW DC power from a 1 V supply. On-chip high quality factor transformers and inductors with small form-factors are used extensively in the receiver to boost gain, interface between stages and provide DC isolation. To optimise the receiver gain and NF with the minimal power consumption, non-unity transformer turn ratio is utilised to enable either voltage or current amplification according to circuit needs.

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A 52 GHz Phased-Array Receiver Front-End in 90 nm Digital CMOS

Cited by 92 publications

References 18 publications

A 28 GHz SiGe PLL for an 81–86 GHz E-band beam steering transmitter and an I/Q phase imbalance detection and compensation circuit

A 28 GHz SiGe PLL for an 81–86 GHz E-band beam steering transmitter and an I/Q phase imbalance detection and compensation circuit

A PLL based 12 GHz LO generator with digital phase control in 90 nm CMOS

65 nm CMOS receiver with 4.2 dB NF and 66 dB gain for 60 GHz applications

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