A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS

Abstract

This paper presents an ultra-lower-power (ULP) digital-to-time-converter (DTC)-assisted fractional-N all-digital phase-locked loop (ADPLL) suitable for IoT applications. A proposed hybrid time-to-digital converter (TDC) extends the vernier-TDC input range with little power overhead in order to overcome the stability issue in the conventional architectures. The hybrid TDC also facilitates a background gain calibration to achieve a stable in-band phase noise insensitive to process, voltage, and temperature (PVT) variations. The implementation of a buffercascaded DTC simplifies the design complexity of the fractional-N operation. The ADPLL also features a 200 µW low-phase-noise inverse-class-F (class-F −1 ) digitally controlled oscillator (DCO) without the need of two-dimensional (2-D) capacitor tuning for frequency alignment of the fundamental and 2 nd -harmonic. Fabricated in 65-nm CMOS, the ULP ADPLL prototype achieves 868 fs rms jitter in a fractional-N channel when consuming only 529 µW, corresponding to a figure-of-merit (FoM) of −244 dB.

Circuit Techniques for Immunity to Process, Voltage, and Temperature Variations in the Attachable Fractional Divider

“…That means a significant amount of time and financial investment are required. Another choice is to replace Int-N PLLs with fractional-N PLLs (Frac-N PLLs) like in [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16], multiplying reference frequency with fractional value. Within this choice, we have a few options: acquiring Frac-N PLLs from a silicon IP developer or developing the necessary PLLs from scratch.…”

“…However, obviously, this requires a significant amount of time to create the necessary PLLs, resulting in increasing time-tomarket. While Frac-N digital PLLs appear to be designed quickly due to their digital-rich structures, most of them need time-to-digital converters (TDCs) to make phase quantization noise small [2][3][4][5]. The TDC, a critical analog block, requires a significant amount of time to develop and needs calibration, increasing complexity.…”

Process and temperature robust time‐difference amplifier with analog calibration

“…Calibration schemes in time-to-digital converters (TDC) usually involve multiple delay cells [1,2] and digital circuits to perform calibration algorithms [3,4] based on PLL phase error information. Using time-difference amplifiers (TA) in TDC can achieve sub-gate-delay resolution while maintaining performance tradeoffs, such as resolution, power, and area consumption.…”