A 56–65 GHz Injection-Locked Frequency Tripler With Quadrature Outputs in 90-nm CMOS

Abstract

A sub-harmonic injection-locked tripler multiplies a 20-GHz differential input to 60-GHz quadrature (I/Q) output signals. The tripler consists of a two-stage ring oscillator driven by a single-stage polyphase input filter and 50-I and Q-signal output buffers. Each gain stage incorporates a hard limiter to triple the input frequency for injection locking and a negative resistance cell with two positive feedback loops to increase gain. Regenerative peaking is also used to optimize the gain/bandwidth performance of the 50-output buffers. Fabricated in 90-nm CMOS, the tripler has a free-running frequency of 60.6 GHz. From a 0-dBm RF source, the measured output lock range is 56.5-64.5 GHz, and the measured phase noise penalty is 9.2 1 dB with respect to a 20.2-GHz input. The 0 3 0 3 mm 2 tripler (including passives) consumes 9.6 mW, while the output buffers consume 14.2 mW, all from a 1-V supply.Index Terms-Frequency tripler, injection-locked, millimeterwave, quadrature voltage-controlled oscillator, regenerative peaking, wide locking range. I. INTRODUCTIONE XCITING new opportunities are envisioned for silicon integrated circuits that are capable of mm-wave operation. Potential consumer applications include: gigabit per second short-range wireless communication in the 60-GHz (defined in the IEEE 802.15.3c standard) and 120-GHz bands, long-range collision avoidance radar for automobiles at 77 and 79 GHz, and sub-terahertz imaging (94 GHz and above) [1]-[3]. Production silicon VLSI technologies have demonstrated a peak transit frequency, , above 200 GHz for bipolar (NPN) devices [4], [5] and higher than 300 GHz for CMOS (NFET) transistors [6], [7], which has focused commercial interest towards millimeter-wave (mm-wave) frequency applications for silicon integrated circuits. Implementation of mm-wave transceivers in baseline CMOS technology is attractive because of its high potential for both low cost in volume production and RF/baseband co-integration.Single-sideband modulation or demodulation in a mm-wave transceiver requires a mm-wave local oscillator (LO) with quadrature (i.e., I and Q) outputs. A phase and amplitude tuning mechanism with about 5 and 0.5 dB [8] of correction range is required in order to tune out the unwanted sideband, as sideband rejection is often degraded by phase and amplitude

Injection‐locked frequency tripler with series‐tuned resonator in 0.13 μm CMOS technology

“…However, the problem can be solved from the perspective of time-domain definition for UWB antennas. Therefore, energy pattern function of UWB antenna array in the time domain can be defined [7]: …”

“…The other common implementation of frequency tripler (doubler) is to generate third (second) harmonic of an input signal using a nonlinear device, and then choose the desired harmonic component by a filter network [5]. Injection-locked frequency multipliers (ILFM) have been studied in the past [1,4,6,7] and these circuits use parallel LC-tank. This article proposes an injection-locked frequency tripler (ILFT) with a series-tuned LC-resonator, the ILFT integrates a first-harmonic injection-locked oscillator (ILO) with a third harmonic generator implemented with transistor.…”

A Frequency Tripler Using a Subharmonic Mixer and Fundamental Cancellation

“…Balanced frequency tripler circuits based on extracting the third harmonic generated by FET nonlinearities are presented in [9] and [10] with on-chip filtering and cancellation of unwanted harmonics, but the required chip area can be very large (e.g., 5.0 mm in [9] and 2.32 mm in [10]). Injection locking can also be used to implement a frequency tripler [11], [12], although the resonator used in the oscillator can consume a large chip area and can limit the bandwidth of the circuit. Recent advances in integrated circuit tripler design [13] have used waveform shaping techniques in order to generate the triple frequency and to relax the output filter requirements.…”

A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications

“…The 20 GHz VCO uses tail-feedback to further lower the phase noise of the 20 GHz PLL through modulation of the tail current. Also, a QILO that avoids the use of polyphase filters [5] to improve I/Q mismatch is proposed. It uses a dual injection topology [6], [7] that improves I/Q mismatch and enhances injection, thus reducing the injection power required for locking.…”