A 56-GS/s 8-bit Time-Interleaved ADC With ENOB and BW Enhancement Techniques in 28-nm CMOS

Sun, Kai; Wang, Guanhua; Zhang, Qing; Elahmadi, Salam; Gui, Ping

doi:10.1109/jssc.2018.2884352

Cited by 58 publications

(19 citation statements)

References 20 publications

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“…Integrated multi-GHz-band lowpass filters are required as antialiasing filters for very high-speed analog-to-digital (ADC) and digital-to-analog (DAC) converters [1] in applications such as wideband spectrum monitoring, high bit-rate optical communications [2,3] and wideband measurement systems [4,5]. They have to be designed in silicon technology to be integrated on the same chip with the converter blocks, thus minimizing off-chip interfaces, and should possibly avoid the use of spiral inductors, to minimize chip area.…”

Section: Introductionmentioning

confidence: 99%

10-GHz Fully Differential Sallen–Key Lowpass Biquad Filters in 55nm SiGe BiCMOS Technology

et al. 2020

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Multi-GHz lowpass filters are key components for many RF applications and are required for the implementation of integrated high-speed analog-to-digital and digital-to-analog converters and optical communication systems. In the last two decades, integrated filters in the Multi-GHz range have been implemented using III-V or SiGe technologies. In all cases in which the size of passive components is a concern, inductorless designs are preferred. Furthermore, due to the recent development of high-speed and high-resolution data converters, highly linear multi-GHz filters are required more and more. Classical open loop topologies are not able to achieve high linearity, and closed loop filters are preferred in all applications where linearity is a key requirement. In this work, we present a fully differential BiCMOS implementation of the classical Sallen Key filter, which is able to operate up to about 10 GHz by exploiting both the bipolar and MOS transistors of a commercial 55-nm BiCMOS technology. The layout of the biquad filter has been implemented, and the results of post-layout simulations are reported. The biquad stage exhibits excellent SFDR (64 dB) and dynamic range (about 50 dB) due to the closed loop operation, and good power efficiency (0.94 pW/Hz/pole) with respect to comparable active inductorless lowpass filters reported in the literature. Moreover, unlike other filters, it exploits the different active devices offered by commercial SiGe BiCMOS technologies. Parametric and Monte Carlo simulations are also included to assess the robustness of the proposed biquad filter against PVT and mismatch variations.

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Section: Introductionmentioning

confidence: 99%

10-GHz Fully Differential Sallen–Key Lowpass Biquad Filters in 55nm SiGe BiCMOS Technology

et al. 2020

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“…Nowadays, with the large amount of internet of thing (IoT) and wideband of 5G-communication technology, the bandwidth of the signals is getting wider and wider. To analyze these wideband signals with complex modulation types, the broadband analog to digital converters (ADCs) [1]- [3] are widely utilized to sampling the signals. The chips related to the sampling systems of the ADCs are widely implemented by GaAs process due to their high-speed characteristics.…”

Section: Introductionmentioning

confidence: 99%

“…Due to the limited conversion speed of a single-channel ADC, time-interleaved technique is widely utilized. For example, paper [3] shows a 56 GS/s ADC with 256 parallel channels and speed of each channel is only several hundred MS/s. With this time-interleaved structure, the high-speed sampling system design challenge moves to front-end THA design and clock distribution.…”

Section: Introductionmentioning

confidence: 99%

A Quadrature PLL With Phase Mismatch Calibration for 32GS/s Time-Interleaved ADC

Ren

2020

IEEE Access

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“…To achieve the highest sampling rates, a time-interleaved ADC (TI-ADC) architecture is used. [7][8][9] The TI-ADC architecture arranges M sub-ADCs operating in parallel, at M times lower sampling rate. In this architecture, one track and hold (T&H) switch is used for each sub-ADC.…”

mentioning

confidence: 99%

“…A hierarchical TI-ADC implementation has been used to alleviate the timing requirements for the T&H, allowing the use of more interleaved channels. [9][10][11] The typical hierarchical TI-ADC topology uses a T&H with two or more ranks of switches and signal buffering between hierarchies, as shown in Figure 1. The signal is sampled in capacitor C s during the tracking time.…”

mentioning

confidence: 99%

A 4GS/s 8‐bit time‐interleaved SAR ADC with an energy‐efficient architecture in 130 nm CMOS

Solis

Bocco

Galetto

et al. 2021

Circuit Theory & Apps

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This paper presents the design, implementation, and measurements of a 4 GS/s, 8-bit resolution, time-interleaved (TI) analog-to-digital converter (ADC) comprised of 32 asynchronous successive approximation register (SAR) ADCs. The chip is fabricated in a 130 nm CMOS process. This prototype achieves the highest sampling rate and the best efficiency for a SAR TI-ADC in the process used. An energy-efficient hierarchical T&H architecture, ranked in a 4 × 8 structure, has been used to interleave the aforementioned high number of SAR ADCs avoiding the power hungry buffers typically used in the input signal path and/or T&H outputs. The sampling architecture includes programmable delay cells with up to 104 fs resolution to calibrate sampling time errors. Additionally, the input matching network uses an on-chip inductance to mitigate the impact of the packaging on the analog bandwidth. An efficient SAR ADC implementation is achieved by an optimized comparator design, which allows for both, noise and asynchronous clock control, and includes background DC offset calibration. The test chip is the core of a measurement platform dedicated to the evaluation of mismatch calibration techniques for ADCs used in high speed digital communication systems. To enable this application, a 32Gb/s low-voltage differential signaling interface is included to transmit the samples off-chip without any decimation. The TI-ADC achieves a peak 7.09 effective number of bits (ENOB) (5.47ENOB at Nyquist) and 1.3 GHz input bandwidth with a power consumption of 93 mW at 1.2 V. Each SAR ADC channel achieves a Walden figure of merit (FOM) of 123fJ/conv-step and owing to the efficient interleaved architecture the full TI-ADC achieves a peak FOM of 171fJ/conv-step (526fJ/conv-step at Nyquist).

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A 56-GS/s 8-bit Time-Interleaved ADC With ENOB and BW Enhancement Techniques in 28-nm CMOS

Cited by 58 publications

References 20 publications

10-GHz Fully Differential Sallen–Key Lowpass Biquad Filters in 55nm SiGe BiCMOS Technology

10-GHz Fully Differential Sallen–Key Lowpass Biquad Filters in 55nm SiGe BiCMOS Technology

A Quadrature PLL With Phase Mismatch Calibration for 32GS/s Time-Interleaved ADC

A 4GS/s 8‐bit time‐interleaved SAR ADC with an energy‐efficient architecture in 130 nm CMOS

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