A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW

Chung, Hoeju; Jeong, Byung Hoon; Min, Byung-Jun; Choi, Yong‐Sang; Cho, Beak-Hyung; Shin, Jun-Ho; Kim, Jin‐Young; Jung, Sunghwan; Park, Joon-Min; Wang, Qi; Lee, Yong-jun; Cha, Sooho; Kwon, Dukmin; Kim, Sangtae; Kim, Sung Hoon; Rho, Yoohwan; Park, Mu-Hui; Kim, Jaewhan; Song, Ickhyun; Jun, Sunghyun; Lee, Jae‐Wook; Kim, KiSeung; Lim, Kiwon; Chung, Won-Ryul; Choi, Chang‐Hwan; Cho, HoGeun; Shin, Inchul; Jun, Woochul; Hwang, Seok-Won; Song, Ki–Whan; Lee, Kwang-Jin; Chang, Sang-whan; Cho, Woo-Yeong; Yoo, Jung-Keun; Jun, Young-Hyun

doi:10.1109/isscc.2011.5746415

Cited by 45 publications

(37 citation statements)

References 2 publications

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“…Recently, real PCM prototypes from several manufacturers have been announced with an LPDDR2-NVM interface [6,7]. The LPDDR2-NVM interface is somewhat similar to conventional DRAM, but at the same time, shows different behavior due to the differences between DRAM and non-volatile memories.…”

Section: Jedec Lpddr2-nvm Industry Standardmentioning

confidence: 99%

“…The timing parameters for PCM, such as cell program time, are varying from 20,000 ns to 150 ns to evaluate the potential of the proposed method, depending on the cell program time. The slowest cell program time of a commercial PCM device with an LPDDR2-NVM interface is 20 ms [6], while the very optimistic cell program time presented in the research prototype is 150 ns [7]. The details of the simulation setup are summarized in Table 1.…”

Section: Experiments 1 Evaluation Setupmentioning

confidence: 99%

“…Most designs concentrated on reducing the number of memory accesses or on optimizing the internal operations within PCM devices, because they assumed an architecture similar to DRAM devices without considering its interface [4,5]. This assumption is partially true, but they overlooked the time consuming interface operation in real industry PCM prototypes equipped with low power double data rate 2 non-volatile memory (LPDDR2-NVM) [6,7]. In addition, most of them assumed too optimistic write operations, which is also far from the industry prototype.…”

Section: Introductionmentioning

confidence: 99%

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Accelerating Memory Access with Address Phase Skipping in LPDDR2-NVM

Park¹,

Shin²,

Chang³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Low power double data rate 2 non-volatile memory (LPDDR2-NVM) has been deemed the standard interface to connect non-volatile memory devices such as phase-change memory (PCM) directly to the main memory bus. However, most of the previous literature does not consider or overlook this standard interface. In this paper, we propose address phase skipping by reforming the way of interfacing with LPDDR2-NVM. To verify effectiveness and functionality, we also develop a system-level prototype that includes our customized LPDDR2-NVM controller and commercial PCM devices. Extensive simulations and measurements demonstrate up to a 3.6% memory access time reduction for commercial PCM devices and a 31.7% reduction with optimistic parameters of the PCM research prototypes in industries.

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Section: Jedec Lpddr2-nvm Industry Standardmentioning

confidence: 99%

Section: Experiments 1 Evaluation Setupmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Accelerating Memory Access with Address Phase Skipping in LPDDR2-NVM

Park¹,

Shin²,

Chang³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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“…PCM [30] is argurably the most mature among all resistive memory technologies, as evidenced by 128Mb parts that are currently in production [16], as well as gigabit array prototypes [51,12]. A PCM cell is formed by sandwiching a chalcogenide phase-change material such as Ge2Sb2T e5 (GST) between two electrodes.…”

Section: Resistive Memory Technologiesmentioning

confidence: 99%

A resistive TCAM accelerator for data-intensive computing

Guo

Bai

et al. 2011

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

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Power dissipation and o↵-chip bandwidth restrictions are critical challenges that limit microprocessor performance. Ternary content addressable memories (TCAM) hold the potential to address both problems in the context of a wide range of data-intensive workloads that benefit from associative search capability. Power dissipation is reduced by eliminating instruction processing and data movement overheads present in a purely RAM based system. Bandwidth demand is lowered by processing data directly on the TCAM chip, thereby decreasing o↵-chip tra c. Unfortunately, CMOSbased TCAM implementations are severely power-and arealimited, which restricts the capacity of commercial products to a few megabytes, and confines their use to niche networking applications.This paper explores a novel resistive TCAM cell and array architecture that has the potential to scale TCAM capacity from megabytes to gigabytes. High-density resistive TCAM chips are organized into a DDR3-compatible DIMM, and are accessed through a software library with zero modifications to the processor or the motherboard. On applications that do not benefit from associative search, the TCAM DIMM is configured to provide ordinary RAM functionality. By tightly integrating TCAM with conventional virtual memory, and by allowing a large fraction of the physical address space to be made content-addressable on demand, the proposed memory system improves average performance by 4⇥ and average energy consumption by 10⇥ on a set of evaluated data-intensive applications.

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“…While phase transition processes are well understood and some PCM chips have been manufactured successfully [5,6], there are still some issues need to be solved. And power consumption is one of the most serious in all the issues.…”

Section: Introductionmentioning

confidence: 99%

Understanding the influence of RESET current due to the active region of phase change memory

Wang

Chen

2017

IEICE Electron. Express

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The RESET current of T-shaped phase change memory (PCM) cells based on Ge 2 Sb 2 Te 5 (GST) with 35 nm heating electrodes has been studied to understand the influences of RESET current due to the active region via Transmission Electron Microscope (TEM) and testing. The results have been presented and analyzed. Based on the TEM images, it is found that the grains inside and outside the active region have different structures for the operated cells. And the RESET current can be effectively reduced by obtaining larger active region with the grains of Face Centered Cubic (FCC), confirmed by the testing results.

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A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW

Cited by 45 publications

References 2 publications

Accelerating Memory Access with Address Phase Skipping in LPDDR2-NVM

Accelerating Memory Access with Address Phase Skipping in LPDDR2-NVM

A resistive TCAM accelerator for data-intensive computing

Understanding the influence of RESET current due to the active region of phase change memory

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