A 6.25 Gb/s equalizer in 0.18 μm CMOS technology for high-speed SerDes

Abstract

This paper presents a 0.18 m CMOS 6.25 Gb/s equalizer for high speed backplane communication. The proposed equalizer is a combined one consisting of a one-tap feed-forward equalizer (FFE) and a two-tap half-rate decision feedback equalizer (DFE) in order to cancel both pre-cursor and post-cursor ISI. By employing an active-inductive peaking circuit for the delay line, the bandwidth of the FFE is increased and the area cost is minimized. CML-based circuits such as DFFs, summers and multiplexes all help to improve the speed of DFEs. Measurement results illustrate that the equalizer operates well when equalizing 6.25 Gb/s data is passed over a 30-inch channel with a loss of 22 dB and consumes 55.8 mW with the supply voltage of 1.8 V. The overall chip area including pads is 0.3 0.5 mm 2 .

Optimization of equalization architecture for the high-speed serial communication

“…From the view of frequency domain, a LE is actually a high-pass filter amplifying the high frequency signal component, there by compensating for the channel attenuation [4] . The transfer function of LE frequency response can be given by: LE boosts the high frequency contents of the signal, however, it also amplifies high frequency noise and crosstalk.…”