A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization

Design Techniques for High-Speed I/Os: Challenges and Opportunities

“…All need to be completed within one UI for tap-1. Loop-unrolling has been proven to be an effective technique in meeting the timing constraint of the tap-1 of DFE [19,[58][59][60]. High-order loop-unrolling also emerged when data rate exceeds 10 Gb/s, however, at the cost of high silicon consumption [10,11,61].…”

“…High-order loop-unrolling also emerged when data rate exceeds 10 Gb/s, however, at the cost of high silicon consumption [10,11,61]. To relax the timing constraint and at the same time to lower the power consumption of the remaining DFE taps, the half rate approach is widely used [59]. Quarter-rate approach was also deployed to further relax the timing constraint, however, at the cost of high silicon consumption [10,11,49,61].…”

On-chip data communication : analysis, optimization and circuit design

“…In such pre-emphasis schemes, delayed copies of the symbols are weighted and summed to create equalizing finite impulse response (FIR) filters [97,98,[111][112][113][114][115][116][117].…”

“…But DFE with more than a few taps tends to become complex and power hungry, so it is sometimes combined with a linear equalizer [111,112,116,137,138]. An often stated motivation is that linear equalizers can cancel long tails in the symbol response with lower complexity.…”

“…When DFE is used at the receiver, an often stated motivation to also use transmitter preemphasis is the statement that transmitter pre-emphasis can correct pre-cursor ISI, while receiver DFE can not [111]. Also, pre-emphasis can cancel long tails in the symbol response with only a few taps (as discussed in section 7.3), while DFE can cancel only as many ISI points as it has taps [111].…”