A 6-b, 4 GSa/s GaAs HBT ADC

Poulton, K.; Knudsen, K.L.; Corcoran, J.J.; Wang, Keh-Chung; Nubling, R.B.; Pierson, R.; Chang, Mau-Chung Frank; Asbeck, P.M.; Huang, Rong‐Ting

doi:10.1109/4.466071

Cited by 44 publications

(5 citation statements)

References 6 publications

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“…8). This structure suppresses the metastability states, by providing more amplification of the input signal and a better conversion speed by holding a state comparison result [11][12][13].…”

Section: Sampling Stagementioning

confidence: 98%

Design of a high-speed CMOS multi-bit quantizer for continuous-time Delta-Sigma Modulator applications

Mariano

Goumballa

Dallet

et al. 2008

Analog Integr Circ Sig Process

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Digital front-end receivers realize direct conversion of an analog signal to digital form at intermediate frequencies (IF), simplifying the overall system design and alleviating the problems associated with IF mixers. The trend is to eliminate any RF/analog mixers and digitize the RF signal as near as possible to the antenna. In order to digitize directly the analog input signal, a high dynamic-range and high-speed ADC is needed. Continuous-Time Bandpass Delta-Sigma Modulator can meet these requirements, using high-performance multi-bit quantizers. This article presents the design of a high-speed CMOS Analog-to-Digital Converter (ADC) which can be used as a quantizer in Continuous-Time Delta-Sigma Modulator. It is designed in a 130 nm CMOS technology from STMicroelectronics. The main features of the ADC are 3-bit resolution with 4 GHz sampling rate in a 0.8-2 GHz bandwidth.

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Section: Sampling Stagementioning

confidence: 98%

Design of a high-speed CMOS multi-bit quantizer for continuous-time Delta-Sigma Modulator applications

Mariano

Goumballa

Dallet

et al. 2008

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

show abstract

“…After each comparator, two D-latches in a masterslave configuration (DFF) perform the sampling function ( Figure 5). This structure suppresses the metastability states, by providing more amplification of the input signal and better conversion speed by holding a state comparison result [7][8][9].…”

Section: Sampling Stagementioning

confidence: 98%

High-speed CMOS analog-to-digital converter for front-end receiver applications

Mariano

Boumballa

Dallet

et al. 2007

Proceedings of the 20th Annual Conference on Integrated Circuits and Systems Design

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Modern front-end receivers perform direct conversion of an analog signal to digital form at intermediate frequencies (IF), simplifying the overall system design and alleviating the problems associated with IF mixers. The final aspiration is to directly digitize the RF signal and hence eliminate any RF/analog mixers. In order to direct digitize the analog input signal, a high dynamic-range and high-speed ADC is needed. Continuous-Time Bandpass Delta-Sigma Modulator can meet these specifications, using high-performance multi-bit quantizers. This article presents the design of a high-speed CMOS Analog-to-Digital Converter (ADC) to be used as a quantizer in modern digital receivers. It is designed in a 130 nm CMOS technology from STMicroelectronics. The main features of the ADC are 3-bit resolution with 4 GHz sample rate in a 0.8-2GHz bandwidth.

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“…Briefly stated, the idea was that to go fast, you should use the fastest technology. In the late 90's, 25-GHz bipolar technology could hit 1.5 GSa/s [1] and 2 GSa/s [2] and 50-GHz GaAs HBT technology reached 4 GSa/s [3]. 8-bit CMOS ADCs were still in the 100-MSa/s range.…”

Section: Th-century Technologies For Gigasample Adcsmentioning

confidence: 99%

ARCHITECTURES AND ISSUES FOR GIGASAMPLE/SECOND ADCs

Poulton

Neff

Setterberg

et al.

Analog Circuit Design

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Architectures for ADCs at 1 Gigasample/second (1 GSa/s) and beyond now include flash, folding and interpolating as well as the time interleaving of slower unit converters such as pipeline and even successive approximation ADCs. In addition, CMOS is taking over in this former bastion of bipolar technology. We describe the issues common to all architectures: bandwidth, power, I/O, data storage, and cost. We examine these issues in detail for the time-interleaved approach as exemplified by two 8-bit ADCs operating at 4 GSa/s and 20 GSa/s, implemented in CMOS.

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A 6-b, 4 GSa/s GaAs HBT ADC

Cited by 44 publications

References 6 publications

Design of a high-speed CMOS multi-bit quantizer for continuous-time Delta-Sigma Modulator applications

Design of a high-speed CMOS multi-bit quantizer for continuous-time Delta-Sigma Modulator applications

High-speed CMOS analog-to-digital converter for front-end receiver applications

ARCHITECTURES AND ISSUES FOR GIGASAMPLE/SECOND ADCs

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