A 6 bit 800MHz TIADC Based on Successive Approximation in 65nm Standard CMOS Process

Salimath, Arunkumar; Debnath, Chandrajit; Chatterjee, Kallol; Mandal, Sushanta K.

doi:10.1109/vlsi.design.2010.55

Cited by 3 publications

(4 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In (5), an average number is calculated to improve the accuracy and simulation results show wn ¼ 3 is adequate for estimating the chirp rate (see Section 4). Once the Xðt; fÞ is derived, the chirp rate can be obtained.…”

Section: The Chirp Rate Estimation Algorithmmentioning

confidence: 99%

“…When these information are known, those sampling systems can first de-chirp the target signal to reduce its bandwidth (the de-chirped signal is formulated as xðtÞ ¼ zðtÞcosð2f 0 tÞ which is always a narrow band signal), then based on the carrier frequency, the de-chirped signal can be acquired at a low rate by Nyquist sampling or bandpass sampling. When the prior information is unavailable, a conventional method of acquiring the chirp signal is to use an ultra-high speed sampling system which satisfies the wellknown Nyquist sampling theorem, for example, the time-interleave analog-todigital converter (TIADC) [4,5,6]. However, the Nyquist sampling theorem is inefficient in many applications, because samples produced by an ultra-high speed sampling system are extremely redundant [7,8,9].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A novel compressive sampling system for chirp signal

Yang

Yan

Qin

2017

IEICE Electron. Express

View full text Add to dashboard Cite

In this letter, a compressive sampling system, which can acquire chirp signal without the prior information of carrier frequency and chirp rate, is proposed. The system first estimates the chirp rate based on windowed modulated wideband converter (MWC). When chirp rate is derived, the system can de-chirp the target signal. Then, the de-chirped signal is acquired by sampling module of the system. Finally, basedon samples, the original signal can be reconstructed by a greedy iteration algorithm which has an adaptive halting condition. Simulation results show the system is capable of estimating chirp rate and reconstructing original signal.

show abstract

Section: The Chirp Rate Estimation Algorithmmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A novel compressive sampling system for chirp signal

Yang

Yan

Qin

2017

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…Small PMOS capacitor arrays are used to dynamically configure the comparator thresholds. Therefore differently from known TI SAR ADC arrays [2][3][4][5][6][7][14][15][16][17] there is no need for a feedback DAC to generate the error signal between the sampled input and the comparator output. This task is performed by the comparator itself.…”

Section: New Sar Adc Channel Designmentioning

confidence: 99%

“…Timeinterleaving of basic ADC channels is also used in literature to design fast converters [2][3][4][5][6][7][14][15][16][17].…”

Section: Introductionmentioning

confidence: 99%

Configurable array of low-complex SAR ADCs

Saponara

2011

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

An array of low-complex SAR ADCs, configurable in time-interleaved (TI) or parallel modes to reach 1 GS/s or to serve multiple inputs at hundreds of MS/s, is proposed in this letter. Each SAR ADC channel exploits a threshold-configuring scheme, to avoid internal DAC thus saving circuit complexity, plus a dynamic comparator which allows for power consumption scalable versus processing speed. Implementation results in 90 nm 1 V CMOS technology are presented and compared to the state of the art

show abstract

A 2GSPS 6-bit Two-Channel-Interleaved Successive Approximation ADC Design in 65nm CMOS

Feng

Zhou

Liu

et al. 2013

2013 International Conference on Computational and Information Sciences

View full text Add to dashboard Cite

This paper presents a two channel interleaved 6-bit 2GS/s successive approximation (SA) analog-to-digital converter design. The proposed SAR-ADC employs different comparators for each stage, which eliminates digital control delay as in conventional design. Using small size of capacitor and pre amplified comparator, the sampling rate limitation has been broken up with which is only related to intrinsic delay of this circuit. Error correction technique and mismatch calibration relax the requirement of comparator which in end minimizes power consumption. It achieves a peak SNDR of 31.8dB and 29.1dB, at 1.5GS/s and 2GS/s, consuming 9.13mW and 12.58mW with a unit capacitance of 15fF.

show abstract

A 6 bit 800MHz TIADC Based on Successive Approximation in 65nm Standard CMOS Process

Cited by 3 publications

References 5 publications

A novel compressive sampling system for chirp signal

A novel compressive sampling system for chirp signal

Configurable array of low-complex SAR ADCs

A 2GSPS 6-bit Two-Channel-Interleaved Successive Approximation ADC Design in 65nm CMOS

Contact Info

Product

Resources

About