A 6-Gb/s Differential Voltage Mode Driver with Independent Control of Output Impedance and Pre-Emphasis Level

Bae, Chong Woo; Choi, Dongho; Ahn, Kang-Soon; Yoo, Changsik

doi:10.5573/jsts.2013.13.5.423

Cited by 2 publications

(2 citation statements)

References 14 publications

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“…In the transmitter, the 20-bit parallel input TDQh0:19i is serialized with the multi-phase clock È CLK h0:3i provided by the main PLL. The serialized data is then driven to the differential data outputs TxP and TxN by a voltage mode driver for low power consumption [13]. …”

Section: Introductionmentioning

confidence: 99%

A 1.5–5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop

Choi

Yoo

2014

IEICE Electron. Express

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A clock and data recovery (CDR) circuit for 1.5-5.0 Gb/s wireline transceiver is described. A phase locked loop (PLL) with dual phase frequency detector (PFD) and charge pump (CP) pairs performs the seamless phase rotation for the CDR circuit to track the phase and frequency difference. The CDR circuit implemented in a 65 nm CMOS process consumes 22.8 mW from a 1.2 V supply at 5.0 Gb/s. For 25 MHz jitter frequency, the CDR circuit can tolerate up to 0.21 unit-interval (UI) jitter with bit error rate (BER) smaller than 10 !12 .

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Section: Introductionmentioning

confidence: 99%

A 1.5–5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop

Choi

Yoo

2014

IEICE Electron. Express

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“…For instance, sensitivity of a sense amplifier is reduced by large threshold voltage variation [1,2]. In feed forward equalization (FFE) transmitters that use a current mode logic (CML) type driver, process variation at current biasing in a driver causes tap coefficient errors which lead to overall FFE performance degradation [2][3][4][5].…”

Section: Introductionmentioning

confidence: 99%

Cost-Efficient and Automatic Large Volume Data Acquisition Method for On-Chip Random Process Variation Measurement

Lee¹,

Han²,

Lee³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper proposes a cost-efficient and automatic method for large data acquisition from a test chip without expensive equipment to characterize random process variation in an integrated circuit. Our method requires only a test chip, a personal computer, a cheap digital-to-analog converter, a controller and multimeters, and thus large volume measurement can be performed on an office desk at low cost. To demonstrate the proposed method, we designed a test chip with a current model logic driver and an array of 128 current mirrors that mimic the random process variation of the driver's tail current mirror. Using our method, we characterized the random process variation of the driver's voltage due to the random process variation on the driver's tail current mirror from large volume measurement data. The statistical characteristics of the driver's output voltage calculated from the measured data are compared with Monte Carlo simulation. The difference between the measured and the simulated averages and standard deviations are less than 20% showing that we can easily characterize the random process variation at low cost by using our costefficient automatic large data acquisition method. Index Terms-Random process variation, costefficient measurement, automatic large volume data acquisition, statistical characterization, current mode logic driver, current mirror array

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A 6-Gb/s Differential Voltage Mode Driver with Independent Control of Output Impedance and Pre-Emphasis Level

Cited by 2 publications

References 14 publications

A 1.5–5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop

A 1.5–5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop

Cost-Efficient and Automatic Large Volume Data Acquisition Method for On-Chip Random Process Variation Measurement

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