A ±6 ms‐Accuracy, 0.68 mm<sup>2</sup>, and 2.21 <i>μ</i>W QRS Detection ASIC

Huang, Sheng‐Chieh; Wang, Huimin; Chen, Wei-Yu

doi:10.1155/2012/809393

Cited by 11 publications

(10 citation statements)

References 57 publications

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“…Thus the filters can be implemented by connecting array structures (consisting of adders, multipliers, and delay elements) continuously [1]. …”

Section: Systolic Array and Its Datapathmentioning

confidence: 99%

“…DSP also does cardiac investigations through electrocardiogram (ECG) and extracts some characteristic parameters like QRS complexes for HRV (Heart Rate Variability) and RR -intervals (interval between two successive R complexes) [1]. …”

Section: Introductionmentioning

confidence: 99%

“…Other than the distributed arithmetic, the design specific systolic array architectures were also utilized to build the filter architecture. In [1], author has demonstrated the systolic array based digital filter for QRS detector of ECG analysis and has come up with common processing element. In [6] author has demonstrated a high speed 4 : 2 compressor architecture for any digital arithmetic integrated circuits.…”

Section: Introductionmentioning

confidence: 99%

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Low Power Systolic Array Based Digital Filter for DSP Applications

Karthick¹,

Valarmathy²,

Prabhu

2015

The Scientific World Journal

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Main concepts in DSP include filtering, averaging, modulating, and correlating the signals in digital form to estimate characteristic parameter of a signal into a desirable form. This paper presents a brief concept of low power datapath impact for Digital Signal Processing (DSP) based biomedical application. Systolic array based digital filter used in signal processing of electrocardiogram analysis is presented with datapath architectural innovations in low power consumption perspective. Implementation was done with ASIC design methodology using TSMC 65 nm technological library node. The proposed systolic array filter has reduced leakage power up to 8.5% than the existing filter architectures.

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“…Thus the filters can be implemented by connecting array structures (consisting of adders, multipliers, and delay elements) continuously [1]. …”

Section: Systolic Array and Its Datapathmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Low Power Systolic Array Based Digital Filter for DSP Applications

Karthick¹,

Valarmathy²,

Prabhu

2015

The Scientific World Journal

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“…Many researchers have proposed the filters, but the suitability to satisfy the design requirement is the challenge. A similar kind of approach was done to achieve the low power in [6], where the processing element of the digital filter, systolic array, was implemented. In this paper we are addressing the issue for the low power filter architecture of the processing block “QRS detector” used in biomedical sensor networks.…”

Section: Bsn Low Power Requirementmentioning

confidence: 99%

“…In this paper, the digital filter architecture is implemented. Figure 1(a) shows the steps involved in detection of QRS complexes and the filter involved in it [6]. …”

Section: Architecturementioning

confidence: 99%

Low Power Adder Based Digital Filter for QRS Detector

Murali

Chitra²,

Manigandan³

2014

The Scientific World Journal

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Most of the Biomedical applications use dedicated processors for the implementation of complex signal processing. Among them, sensor network is also a type, which has the constraint of low power consumption. Since the processing elements are the most copiously used operations in the signal processors, the power consumption of this has the major impact on the system level application. In this paper, we introduce low power concept of transistor stacking to reduce leakage power; and new architectures based on stacking to implement the full adder and its significance at the digital filter level for QRS detector are implemented. The proposed concept has lesser leakage power at the adder as well as filter level with trade-off in other quality metrics of the design. This enabled the design to be dealt with as the low-power corner and can be made adaptable to any level of hierarchical abstractions as per the requirement of the application. The proposed architectures are designed, modeled at RTL level using the Verilog-HDL, and synthesized in Synopsys Design Compiler by mapping the design to 65 nm technology library standard cells.

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Design of efficient fractional operator for ECG signal detection in implantable cardiac pacemaker systems

Kumar

Komaragiri

Kumar

2019

Circuit Theory & Apps

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Summary A low power and high‐performance digital electrocardiogram (ECG) detector has become a basic requirement in modern implantable cardiac pacemakers. A fractional operator‐based digital ECG detector for modern pacemaker systems is proposed in this work. Instead of conventional thresholding, an adaptive slope prediction threshold is utilized for the detection of ECG peaks. A stochastic search‐based algorithm, namely, cuckoo search algorithm, is used to design an optimal fractional operator that is used for ECG denoising. It has been found that the proposed adaptive slope prediction threshold increases the QRS complex detection performance. A low detection error rate (DER) ranges from 0.01% to 0.56%, positive predictivity (P+) ranges from 99.32% to 99.98%, sensitivity (Se) ranges from 99.45% to 99.98%, and a detection accuracy (Acc) ranges from 99.43% to 99.96% for different databases are achieved for the proposed ECG detector, which is better compared with the existing ECG detectors. The proposed design of fractional order operator based on the lattice wave digital filter (LWDF) requires a minimum number of the multipliers for its structural realization.

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A ±6 ms‐Accuracy, 0.68 mm², and 2.21 μW QRS Detection ASIC

Cited by 11 publications

References 57 publications

Low Power Systolic Array Based Digital Filter for DSP Applications

Low Power Systolic Array Based Digital Filter for DSP Applications

Low Power Adder Based Digital Filter for QRS Detector

Design of efficient fractional operator for ECG signal detection in implantable cardiac pacemaker systems

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A ±6 ms‐Accuracy, 0.68 mm2, and 2.21 μW QRS Detection ASIC

Cited by 11 publications

References 57 publications

Low Power Systolic Array Based Digital Filter for DSP Applications

Low Power Systolic Array Based Digital Filter for DSP Applications

Low Power Adder Based Digital Filter for QRS Detector

Design of efficient fractional operator for ECG signal detection in implantable cardiac pacemaker systems

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Product

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A ±6 ms‐Accuracy, 0.68 mm², and 2.21 μW QRS Detection ASIC