A 6-phase harmonic rejection down-converter with digital assist

Abstract

A down-converter insensitive to 2 nd and 3 rd harmonics and a digital assisting circuit that cancels residual sensitivity due to device mismatches are proposed. Measured 2 nd and 3 rd harmonic rejection ratios of over 60 dB are achieved. This performance allows a simple RF filter, and it is effective to reduce the die size. IntroductionBroad band receivers have a design issue of avoiding harmonic mixing [1][2][3]. In a traditional balanced mixer, the switching operation by the LO signal generates the odd harmonics; while the even harmonics are suppressed because of the balanced circuits structure. As the results, RF signals at the odd multiple frequencies are down-converted to the baseband.There are two attractive down-conversion techniques for the harmonic rejection. One is the double-quadrature mixing (DQM) [1] that executes multiplication of two complex signals. DQM requires RF/IF poly-phase filters as phase-shifters, and the filters occupy large area.The other one is the poly-phase mixing [2]. A conventional poly-phase down-converter consists of weighted-gain mixers driven by 8-phase LO signals. The reduction ratio is limited around 30dB because of gain mismatch. A digital assisting technique that enlarges the reduction with 8-phase mixing was proposed [3]. However, the digital assisting system is able to cancel only a single (3rd or 5th) harmonic, and even harmonics are assumed to be sufficiently rejected only with device matching. We propose a harmonic rejection down-converter with digital assist to eliminate 2 nd and 3 rd harmonics.

Current-Steering Digital-to-Analog Converter With a High-PSRR Current Switch

“…Since the 16-MHz PSN is assumed, two spurious appear on both sides of the fundamental signal at a 16-MHz interval because they are modulated. In this simulation, a parallel digital signal processing or a digital intermediate frequency transmitter architecture [4], [5] is assumed, and thus, the frequency of the input signal is set to around 60 MHz, which is higher than the Nyquist frequency of the digital clock of 16 MHz. The results show that the SFDR using the proposed current switch is improved by about 20 dB.…”

“…The use of an upsampler and an IPF lowers the cost of an analog reconstruction filter (RCF) following a DAC in a scaled CMOS process [2]- [5]. Power-supply noise (PSN) comes from the digital circuit through the common substrate and degrades the spurious-free dynamic range (SFDR) at the DAC's output.…”