A 60 GHz fully differential LNA in 90 nm CMOS technology

Abstract

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm 2 pads included. The detailed design procedure and the achieved measurement results are presented in this work.

A low noise fully differential 60 GHz CMOS active down converter with resonating current bleeding

“…4, have been introduced as source degeneration for stability reasons, while L M performs the common mode rejection. The transistors M T have then been sized with a total gate width of 36 µm, 12 fingers each 3 µm wide, since this size has been found giving a good compromise between noise figure and gain [4]. The gate bias voltage has been adjusted to be the same as the sources DC voltage of the switching quad, in order to reduce the number of DC pads and ease the layout.…”

A CMOS power amplifier using split input and output transformers to minimize its chip area

“…With rapid development of wireless communications for the Internet of Things (IoT), RF integrated circuits (ICs) with compact chip size have become essential to reduce the unit cost of production . To realize compact chip area, a power amplifier should be designed using a CMOS process by which the analog and digital circuits are integrated .…”