A 60 GHz switched-line type phase shifter using body-floating switches

Gul, Muhammad Talha; Duong, H.V.; Kim, Seong-Yeon; Lee, Jong‐Wook

doi:10.1109/isocc.2013.6864048

Cited by 9 publications

(1 citation statement)

References 7 publications

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“…As presented in the literature, there are different types of phase shifters which are classified as active or passive, with either analog or digital set-up. Examples of these phase shifters currently in use are line-load, reflection-type, vector-sum and line-switch [6]- [9]. Active phase shifters (APS) provide a very high degree of integration, smaller amplitude variations and no insertion losses but they need high power consumption in comparison to the passive phase shifters (PPS).…”

Section: Introductionmentioning

confidence: 99%

Analysis and design of an innovative 19.5 GHz active phase shifter architecture, implemented in a 0.13 μm BiCMOS SiGe:C process, for beamforming in 5G applications

Muhammad,

Cordeau,

Paillot

2024

Preprint

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This paper presents the design and implementation of a 19.5 GHz active phase shifter for beamforming. The proposed circuit is based on an original architecture using an injection-locked voltage-controlled oscillator (ILVCO) associated with a polyphase filter followed by a phase selection circuit and its sign. From a 1.3 V supply voltage, the proposed circuit was designed to obtain a phase shift range of 360°. This phase shifter is synthesized using the phase selection circuit (PS) for coarse adjustment in the steps of 90° and the injection-locked VCO for a fine-tuning adjustment between ±45°. The circuit consumed a total current of 20.47 mA with a chip size of 1.51 mm2 including the pads and it is integrated in a BiCMOS SiGe:C 0.13 µm process.

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Section: Introductionmentioning

confidence: 99%

Analysis and design of an innovative 19.5 GHz active phase shifter architecture, implemented in a 0.13 μm BiCMOS SiGe:C process, for beamforming in 5G applications

Muhammad,

Cordeau,

Paillot

2024

Preprint

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A high DC-gain modified CMOS OTA

Lee

Dadashi

Lee

2013

2013 International SoC Design Conference (ISOCC)

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A new operational transconductance amplifier (OTA) based on the conventional triple folded cascode (TFC) structure is presented. Using the proposed method, the DC gain enhances by adding only three positive feedback devices to the TFC structure. The simulation results for the designed OTA in a typical 0.35μm CMOS technology show 20dB DC gain enhancement of conventional TFC while bandwidth, output voltage swing range, and the phase margin of conventional TFC are not affected. Higher linearity in the larger output voltage swings is the other advantages of proposed approach in comparison to previously reported positive feedback methods.Index Terms-positive feedback device (PFD); linearity; triple folded cascode; dc-gain INTRODUCTIONOperational amplifier is one of the basic and important circuits which has a wide range of applications in several analog circuits, such as filters and data converters, etc. The rapid demand for high speed and high resolution applications such as ADCs and DACs results in an increasing demand for high speed and high gain OTAs. For high-accuracy circuits, OTAs with very high open loop gain and high unity gain frequency are required in order to meet both accuracy and fast settling requirements. Satisfying both of these requirements is difficult with short-channel CMOS processes, since the intrinsic gain of the devices is limited. The new structure proposed in this paper is based on the conventional TFC amplifier. TFC amplifiers have been used in several applications especially where the lower output voltage swing range is not an important factor (e.g. [1]). To increase the dcgain of the TFC amplifier a new method is introduced that uses positive feedback and bulk amplification concepts.

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