A 60 GS/s 8-b DAC with &gt; 29.5dB SINAD up to Nyquist frequency in 7nm FinFET CMOS

Greshishchev, Y.M.; Wen, Tingjun; Ben-Hamida, Naim; Aguirre, J.; Aouini, Sadok; Besson, Marinette; Gibbins, Robert; Gouk, Cho Young; Lam, Jerry; McPherson, D.S.; Parvizi, Mahdi

doi:10.1109/bcicts45179.2019.8972740

Cited by 8 publications

(1 citation statement)

References 6 publications

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“…The downside of this approach is the additional overhead requirement of a bulky and power-hungry electronic DAC (EDAC) for the n-bit driving of the modulator, making this scheme a less appealing solution as an EDAC alternative. The power consumption of typical 8-bit EDACs ranges from 0.56 to 4.03 W for 60 to 100 GS/sec sampling rates, respectively [23,24]. Nevertheless, a direct-digital-drive approach could alleviate the need for additional EDACs, to some extent, despite the demand for a digital memory lookup table to deal with non-linearity issues [6].…”

Section: Figurementioning

confidence: 99%

Scalable Photonic Digital-to-Analog Converters

Masnad,

Safaee,

Najeeb

et al. 2024

Photonics

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This work introduces a novel architecture for implementing a parallel coherent photonic digital-to-analog converter (PDAC), designed to transform parallel digital electrical signals into corresponding analog optical output, convertible to analog electrical signals using photodiodes. The proposed architecture incorporates microring resonator-based modulators (MRMs), phase shifters, and symmetric multimode interference couplers. Efficient modulation is achieved by MRMs utilizing carrier depletion-induced refractive index changes, while metal heaters facilitate tuning of the ring resonator resonance wavelength. The proposed architecture is scalable to higher bit resolutions and exhibits a dynamic range limited by MRM’s sensitivity to applied bias and noise levels. Experimental results of the fabricated chip in the silicon-on-insulator (SOI) platform showcase the successful realization of a 4 GSample/sec conversion rate in a 2-bit resolution operation, along with a stationary conversion of four parallel DC digital signals into 16 analog intensity levels in a 4-bit PDAC configuration. The study encompasses a proof-of-concept experimental demonstration of 8 Gbps data conversion, along with a 50 Gbps data conversion rate using the optimized design in the simulation, affirming the accuracy and quality of the PDAC architecture. These findings contribute to the advancement of PDAC technology, providing insights into performance characteristics, limitations, and potential applications.

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Section: Figurementioning

confidence: 99%