A 60-MHz 64-tap echo canceller/decision-feedback equalizer in 1.2- mu m CMOS for 2B1Q high bit-rate digital subscriber line transceivers

Samueli, H.; Joshi, R.B.; Wong, B.C.; Daneshrad, Babak; Tan, Li; Kruse, D.; Nicholas, H.T.

doi:10.1109/cicc.1991.164060

Cited by 3 publications

(1 citation statement)

References 2 publications

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“…Again, the bit parallel computing scheme is adopted and accelerated via carry look ahead adder. In [6,7], a 64 tap CMOS echo canceller & Decision feedback equalizer is presented. Since the computation overhead of update 64 coefficients is relatively high, a sign LMS algorithm is used to reduced the computing complexity.…”

Section: Previous Workmentioning

confidence: 99%

A high throughput rate and low circuit complexity QAM channel equalizer design based on bit serial scheme

Hwang

Lin²

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)

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In this paper, a novel VLSI design for an all digital QAM channel equalizer is presented. We adopted a decision-feedback equalizer (DFE) structure to combat the inter-symbol-interference (ISI) induced during high speed data communication. The equalizer consists mainly of eight transversal adaptive filters and slicers. Since the adaptive filter along with the slicer will form a nonlinear feedback path, the resultant recursive computing often leads to a severe performance bottleneck. To overcome this, a bit serial, MSB first computing scheme based on distributed arithmetic and signed digit number system techniques was developed. In our scheme, the next symbol's equalization can be started as soon as the MSD of the current symbol is obtained. This leads to a computation overlap between successive symbol's equalization and can effectively improve the baud rate. The circuit complexity, however, is still kept low with the help of fine grain pipelining. With careful arrangement of data flow, an efficient systolic array design with 100% utilization and suitable for VLSI implementation is derived. The design architecture is also scalable in that the initiation interval between the processing of two consecutive symbols is a constant of 5 + r d 4 1 clocks (in the delayed sign LMS case) and the hardware complexity is of order 2 . m . (n + 1) , where m and n are tap order and word length.

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Section: Previous Workmentioning

confidence: 99%

A high throughput rate and low circuit complexity QAM channel equalizer design based on bit serial scheme

Hwang

Lin²

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)

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A 35 Mb/s mixed-signal decision-feedback equalizer for disk drives in 2-μm CMOS

Brown¹,

Hurst²,

Der

1996

IEEE J. Solid-State Circuits

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A transceiver for 800 kb/s full-duplex transmission over digital subscriber loops using a custom VLSI adaptive filter processor

Itri¹,

Brackert²,

Nicholas³

et al.

1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers

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We present the design of a bidirectional 800kbls transceiver that enables data transmission for T1 services over unconditioned telephone wire facilities. The transceiver transmits a 4-level PAM line code (2BlQ) and uses a baud-spaced sampled receiver. Our IXP-based transceiver utilizes a custom CMOS V U 1 64-tap LMS adaptive filter chip IO provide echo cancellation and decision-feedback equalization. Error-free full-duplex transmission is achieved over 16 kft. of 24 AWG cable or 12 kft. of 26 AWG cable.

show abstract

A 60-MHz 64-tap echo canceller/decision-feedback equalizer in 1.2- mu m CMOS for 2B1Q high bit-rate digital subscriber line transceivers

Cited by 3 publications

References 2 publications

A high throughput rate and low circuit complexity QAM channel equalizer design based on bit serial scheme

A high throughput rate and low circuit complexity QAM channel equalizer design based on bit serial scheme

A 35 Mb/s mixed-signal decision-feedback equalizer for disk drives in 2-μm CMOS

A transceiver for 800 kb/s full-duplex transmission over digital subscriber loops using a custom VLSI adaptive filter processor

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