A 600-MHz VLIW DSP

Agarwala, S.; Anderson, Timothy R.; Hill, Anthony; Ales, M.D.; Damodaran, R.; Wiley, P.; Mullinnix, S.; Leach, Janice; Lell, Anthony; Gill, Michael; Rajagopal, Arjun; Chachad, A.; Agarwala, M.; Apostol, J.; Krishnan, M.; Bui, Duc; An, Quang; Nagaraj, N.S.; Wolf, T.; Elappuparackal, T.T.

doi:10.1109/jssc.2002.803954

Cited by 59 publications

(22 citation statements)

References 4 publications

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“…Conventional single-threaded RISCs or VLIW DSPs [3] are even worse than this. In contrast, the extensive data-level parallelism (DLP) of GPU [4] or multi-core processors [5] which integrate multiple single instruction multiple data (SIMD) or single instruction multiple thread (SIMT) processing units, enable them to achieve high computing power of 100s of giga floating operation per second (GFLOPS), although at the cost of high power consumption approaching 200 W, which is far beyond power budgets of a mobile vision system.…”

Section: Dbmmentioning

confidence: 99%

A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams

Kim

Park

et al. 2013

IEEE J. Solid-State Circuits

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Abstract-A heterogeneous multi-core processor is proposed to achieve real-time dynamic object recognition on HD 720p video streams. The context-aware visual attention model is proposed to reduce the required computing power for HD object recognition based on enhanced attention accuracy. In order to realize real-time execution of the proposed algorithm, the processor adopts a 5-stage task-level pipeline that maximizes the utilization of its 31 heterogeneous cores, comprising four simultaneous multithreading feature extraction clusters, a cache-based feature matching processor and a machine learning engine. Dynamic resource management is applied to adaptively tune thread allocation and power management during execution based on the detected amount of tasks and hardware utilization to increase energy efficiency. As a result, the 32 mm chip, fabricated in 0.13 m CMOS technology, achieves 30 frame/sec with 342 8-bit GOPS peak performance and 320 mW average power dissipation, which are a 2.72 times performance improvement and 2.54 times per-pixel energy reduction compared to the previous state-of-the-art.Index Terms-Multi-core processor, object recognition, scale invariant feature transform, heterogeneous, low power processor, dynamic resource management, dynamic voltage and frequency scaling. GLOSSARY OF ABBREVIATIONS GOPS

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Section: Dbmmentioning

confidence: 99%

A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams

Kim

Park

et al. 2013

IEEE J. Solid-State Circuits

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“…For example, the TI C64x [4] and third generation Itanium processor [5] use approximately 75% and 70% of their area for memory respectively. Since large memories dissipate more energy and require larger delays per transaction, we seek architectures that minimize the need for memory and keep data near or within processing elements.…”

Section: Small Memorymentioning

confidence: 99%

“…• Small memories and simple single-issue architecture for each processor achieves high energy efficiency. Since large memories-which are normally used in modern processors [4,5]-dissipate significant energy and require larger delays per memory transaction, architectures that minimize the need for memory and keep data near or within processing elements are likely to be more efficient. Along with reduced memory sizes, the datapath and control logic complexity of AsAP are also reduced.…”

Section: Introductionmentioning

confidence: 99%

Architecture and Evaluation of an Asynchronous Array of Simple Processors

Meeuwsen

Apperson

et al. 2008

J Sign Process Syst Sign Image Video Technol

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This paper presents the architecture of an asynchronous array of simple processors (AsAP), and evaluates its key architectural features as well as its performance and energy efficiency. The AsAP processor calculates DSP applications with high energyefficiency, is capable of high-performance, is easily scalable, and is well-suited to future fabrication technologies. It is composed of a two-dimensional array of simple single-issue programmable processors interconnected by a reconfigurable mesh network. Processors are designed to capture the kernels of many DSP algorithms with very little additional overhead. Each processor contains its own tunable and haltable clock oscillator, and processors operate completely asynchronously with respect to each other in a globally asynchronous locally synchronous (GALS) fashion. A 6 × 6 AsAP array has been designed and fabricated in a 0.18 μm CMOS technology. Each processor occupies 0.66 mm 2 , is fully functional at a clock rate of 520-540 MHz at 1.8 V, and dissipates an average of 35 mW per processor at 520 MHz under typical conditions while executing applications such as a JPEG encoder core and a complete IEEE 802.11a/g wireless LAN baseband transmitter. Most processors operate at over 600 MHz at 2.0 V. Processors dissipate 2.4 mW at 116 MHz and 0.9 V. A single AsAP processor occupies 4% or less area than a single processing element in other multi-processor chips. Compared to several RISC processors (single issue MIPS and ARM), AsAP achieves performance 27-275 times greater, energy efficiency 96-215 times greater, while using far less area. Compared to the TI C62x high-end DSP processor, AsAP achieves performance 0.8-9.6 times greater, energy efficiency 10-75 times greater, with an area 7-19 times smaller. Compared to ASIC implementations, AsAP achieves performance within a factor of 2-5, energy efficiency within a factor of 3-50, with area within a factor of 2.5-3. These data are for varying numbers of AsAP processors per benchmark.

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“…The Stratix [16] is an FPGA solution with dedicated embedded FFT logic usign Altera Megacore function. The TI C6416 [17] is a digital signal processor and the Imagine [18] is a media processor. They were both created using pseudo-custom data path tiling.…”

Section: Performance Analysismentioning

confidence: 99%

Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform

Pitkänen

Makinen

Heikkinen

et al. 2006

Lecture Notes in Computer Science

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Abstract. Transport Triggered Architecture (TTA) offers a cost-effective tradeoff between the size and performance of ASICs and the programmability of general-purpose processors. This paper presents a study where a high performance, low power TTA processor was customized for a 1024-point complexvalued fast Fourier transform (FFT). The proposed processor consumes only 1.55 µJ of energy for a 1024-point FFT. Compared to other reported FFT implementations with reasonable performance, the proposed design shows a significant improvement in energy-efficiency.

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A 600-MHz VLIW DSP

Cited by 59 publications

References 4 publications

A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams

A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams

Architecture and Evaluation of an Asynchronous Array of Simple Processors

Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform

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