A 63 μg/√Hz Noise Floor and 14 pJ Power Efficiency Open-Loop MEMS Capacitive Accelerometer Using Closed-Loop Hybrid Dynamic Amplifier

Zhong, Longjie; Liu, Shubin; Xu, Donglai; Zhu, Zhangming

doi:10.1109/tcsi.2023.3236369

Cited by 9 publications

(1 citation statement)

References 51 publications

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“…With the continuous development of electronic science and technology since humankind entered the electronic information age, whether, in the defense or civilian context, the demand for electronic products is getting higher and higher, especially in the portable consumer electronics market, which is rising in the general situation. The renewal of electronic products and the rapid development of mixed-signal systems are increasingly demanding [16][17][18]. The sensor can be regarded as a device that forms the interface between non-electrical physical domains and the electrical domain.…”

Section: Introductionmentioning

confidence: 99%

Study of a High-Precision Read-Out Integrated Circuit for Bridge Sensors

Li,

Wang,

et al. 2023

Micromachines

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Bridge sensors are widely used in military and civilian fields, and their demand gradually increases each year. Digital sensors are widely used in the military and civilian fields. High-precision and low-power analog-to-digital converters (ADCs) as sensor read-out circuits are a research hotspot. Sigma-delta ADC circuits based on switched-capacitor topology have the advantages of high signal-to-noise ratio (SNR), good linearity, and better compatibility with CMOS processes. In this work, a fourth-order feed-forward sigma-delta modulator and a digital decimation filter are designed and implemented with a correlated double sampling technique (CDS) to suppress pre-integrator low-frequency noise. This work used an active pre-compensator circuit for deep phase compensation to improve the system’s stability in the sigma-delta modulator. The modulator’s local feedback factor is designed to be adjustable off-chip to eliminate the effect of process errors. A three-stage cascade structure was chosen for the post-stage digital filter, significantly reducing the number of operations and the required memory cells in the digital circuit. Finally, the layout design and engineering circuit were fabricated by a standard 0.35 μm CMOS process from Shanghai Hua Hong with a chip area of 9 mm2. At a 5 V voltage supply and sampling frequency of 6.144 MHz, the modulator power consumption is 13 mW, the maximum input signal amplitude is −3 dBFs, the 1 Hz dynamic range is about 118 dB, the modulator signal-to-noise ratio can reach 110.5 dB when the signal bandwidth is 24 kHz, the practical bit is about 18.05 bits, and the harmonic distortion is about −113 dB, which meets the design requirements. The output bit stream is 24 bits.

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Section: Introductionmentioning

confidence: 99%