2017
DOI: 10.1088/1748-0221/12/05/c05004
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A 64-channel integrated circuit for signal readout from coordinate detectors

Abstract: A: A specialized integrated circuit was developed for the readout of signal from coordinate detectors of different types, including gas micro-pattern detectors and silicon microstrip detectors. The ASIC includes 64 channels, each containing a low-noise charge-sensitive amplifier with a connectable feedback capacitor and resistor, and fast reset of the feedback capacitor. Each channel of the ASIC also contains 100 cells of analogue memory where the signal can be stored at a rate of 10 MHz. The pitch of input pa… Show more

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Cited by 7 publications
(5 citation statements)
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“…Figure 8 shows the chip design from the engineering CAD software and the schematic of one channel. The electronic calibration of the FE board channel was made and results complied to the previous study of the DMXG64 ASIC [8] (figure 9).…”
Section: Dmxg6asicmentioning
confidence: 69%
See 1 more Smart Citation
“…Figure 8 shows the chip design from the engineering CAD software and the schematic of one channel. The electronic calibration of the FE board channel was made and results complied to the previous study of the DMXG64 ASIC [8] (figure 9).…”
Section: Dmxg6asicmentioning
confidence: 69%
“…The DMXG64 ASIC [8] was developed in Budker Institute of Nuclear Physics for various GEMbased detectors. It has 64 input channels, while each channel has low-noise charge sensitive amplifier and dedicated analog memory for 100 samples.…”
Section: Dmxg6asicmentioning
confidence: 99%
“…As the next step we plan to develop new front-end board, adapted to the pitch of 50 µm unlike the present electronics. The new electronics will use an ASIC, that will be specially designed for this application, and will be based on modified version of DMXG64B integrated circuit [14]. In order to increase quantum efficiency we are going to try a sensor based on GaAs.…”
Section: Summary and Future Plansmentioning
confidence: 99%
“…This pipeline shift register can be operated with a frequency of 10 MHz. Due to limited amount of APC128 chips and expecting better parameters from alternatives, future designs will be based on DMXG64 ASIC which was developed at the BINP [10].…”
Section: Apc128 Front-end Chipmentioning
confidence: 99%