2008
DOI: 10.1109/jssc.2008.2004534
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A 64 mW High Picture Quality H.264/MPEG-4 Video Codec IP for HD Mobile Applications in 90 nm CMOS

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Cited by 17 publications
(9 citation statements)
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“…Practical hardware architectures for real-time video applications [25,26] are often designed to work using a specific parallel granularity (typically MB level, slice level or frame level). To guarantee real-time processing, video processing algorithms are partitioned into several tasks and mapped into a specific parallel structure based on their computing requirements.…”
Section: Basic Processing Unitmentioning
confidence: 99%
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“…Practical hardware architectures for real-time video applications [25,26] are often designed to work using a specific parallel granularity (typically MB level, slice level or frame level). To guarantee real-time processing, video processing algorithms are partitioned into several tasks and mapped into a specific parallel structure based on their computing requirements.…”
Section: Basic Processing Unitmentioning
confidence: 99%
“…(25)) and the relationship between computational complexity and PMV deviation (Eq. (22)), the computation budgett i;j k ð Þ allocated for the ith MB in the jth BPU are determined based on the square of PMV deviations, the average computational complexity and the available remaining computation budget, and can be calculated bŷ…”
Section: Computation-constrained Dsr Controlmentioning
confidence: 99%
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“…They are designed for one specific application for either HD video with high video resolution or portable video with smaller video resolution. Another dual-mode video codec design [10] supporting H.264/MPEG-4 not only satisfied HD720 (1280 × 720) video encoding, but also achieved the low power consumption. However, it was still designed for middle or high video resolution with good picture quality.…”
Section: So/iec Moving Picture Experts Group (Mpeg) Andmentioning
confidence: 99%