A 640M pixel/s 3.65mW sparse event-driven neuromorphic object recognition processor with on-chip learning

Kim, Jung Kuk; Knag, Phil; Chen, Thomas; Zhang, Zhengya

doi:10.1109/vlsic.2015.7231323

Cited by 61 publications

(31 citation statements)

References 3 publications

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“…A switched-capacitor analog implementation has also been proposed to ease robust analog design in deep submicron technologies [26], [27]. However, in order to fully leverage technology scaling, several research groups recently started designing digital SNNs (e.g., Seo et al in [28], Kim et al in [29], IBM with TrueNorth [30] and Intel with Loihi [31]). Digital designs have a shorter design cycle, low sensitivity to noise, process-voltage-temperature (PVT) variations and mismatch, and suppress the need to generate bias currents and voltages.…”

Section: Introductionmentioning

confidence: 99%

A 0.086-mm<formula> <tex>$^2$</tex> </formula> 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOS

Frenkel

Lefebvre

Legat

et al. 2018

IEEE Trans. Biomed. Circuits Syst.

189

149

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Shifting computing architectures from von Neumann to event-based spiking neural networks (SNNs) uncovers new opportunities for low-power processing of sensory data in applications such as vision or sensorimotor control. Exploring roads toward cognitive SNNs requires the design of compact, low-power and versatile experimentation platforms with the key requirement of online learning in order to adapt and learn new features in uncontrolled environments. However, embedding online learning in SNNs is currently hindered by high incurred complexity and area overheads. In this work, we present ODIN, a 0.086-mm 2 64ksynapse 256-neuron online-learning digital spiking neuromorphic processor in 28nm FDSOI CMOS achieving a minimum energy per synaptic operation (SOP) of 12.7pJ. It leverages an efficient implementation of the spike-driven synaptic plasticity (SDSP) learning rule for high-density embedded online learning with only 0.68µm 2 per 4-bit synapse. Neurons can be independently configured as a standard leaky integrate-and-fire (LIF) model or as a custom phenomenological model that emulates the 20 Izhikevich behaviors found in biological spiking neurons. Using a single presentation of 6k 16×16 MNIST training images to a single-layer fully-connected 10-neuron network with on-chip SDSP-based learning, ODIN achieves a classification accuracy of 84.5% while consuming only 15nJ/inference at 0.55V using rank order coding. ODIN thus enables further developments toward cognitive neuromorphic devices for low-power, adaptive and lowcost processing.Index Terms-Neuromorphic engineering, spiking neural networks, synaptic plasticity, online learning, Izhikevich behaviors, phenomenological modeling, event-based processing, CMOS digital integrated circuits, low-power design.

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Section: Introductionmentioning

confidence: 99%

A 0.086-mm<formula> <tex>$^2$</tex> </formula> 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOS

Frenkel

Lefebvre

Legat

et al. 2018

IEEE Trans. Biomed. Circuits Syst.

189

149

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show abstract

“…An analysis of the energy, area and accuracy tradeoffs is shown in Fig. 14 Kim et al [44], from Buhler et al [45] and TrueNorth, which was benchmarked on MNIST in [46]. In order to carry out comparison in a one-to-one basis, all area and energy numbers have been normalized to a 65-nm technology node.…”

Section: Tradeoff Analysis Of Energy Area and Accuracymentioning

confidence: 99%

MorphIC: A 65-nm 738k-Synapse/mm$^2$ Quad-Core Binary-Weight Digital Neuromorphic Processor With Stochastic Spike-Driven Online Learning

Frenkel

Legat

Bol

2019

IEEE Trans. Biomed. Circuits Syst.

141

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Recent trends in the field of neural network accelerators investigate weight quantization as a means to increase the resource-and power-efficiency of hardware devices. As full on-chip weight storage is necessary to avoid the high energy cost of off-chip memory accesses, memory reduction requirements for weight storage pushed toward the use of binary weights, which were demonstrated to have a limited accuracy reduction on many applications when quantization-aware training techniques are used. In parallel, spiking neural network (SNN) architectures are explored to further reduce power when processing sparse eventbased data streams, while on-chip spike-based online learning appears as a key feature for applications constrained in power and resources during the training phase. However, designing power-and area-efficient spiking neural networks still requires the development of specific techniques in order to leverage onchip online learning on binary weights without compromising the synapse density. In this work, we demonstrate MorphIC, a quadcore binary-weight digital neuromorphic processor embedding a stochastic version of the spike-driven synaptic plasticity (S-SDSP) learning rule and a hierarchical routing fabric for large-scale chip interconnection. The MorphIC SNN processor embeds a total of 2k leaky integrate-and-fire (LIF) neurons and more than two million plastic synapses for an active silicon area of 2.86mm 2 in 65nm CMOS, achieving a high density of 738k synapses/mm 2 . MorphIC demonstrates an order-of-magnitude improvement in the area-accuracy tradeoff on the MNIST classification task compared to previously-proposed SNNs, while having no penalty in the energy-accuracy tradeoff.

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“…We also compare our work with a wider range of implementations, including custom ASIC chips [8,41,50,59], neural processing units [18], spiking neural networks [14,28,42], crossbar implementations [57], and CPU/GPU-based solutions of the DropConnect approach [58] (the most accurate approach for MNIST to date; data is measured via i7-5820K, 32GB DDR3 with Nvidia Titan). Fig.…”

Section: Comparison To Other Mnist Implementationsmentioning

confidence: 99%

“…To improve the delay and energy e ciency of computational tasks related to both inference and training, the hardware design and architecture communities are considering how hardware can best be employed to realize algorithms/models from the machine learning community. Approaches include application speci c circuits (ASICs) to accelerate deep neural networks (DNNs) [50,59] and convolutional neural networks (CoNNs) [41], neural processing units (NPUs) [18], hardware realizations of spiking neural networks [14,28], etc.…”

Section: Introductionmentioning

confidence: 99%

“…Besides CeNN cells and SRAM to store weights, the architecture includes analog memory to store intermediate feature map data, and ADC and digital circuits for the FC layer computation. e architecture also supports e cient programming/reprogramming CeNN cells.We have conducted detail studies of energy, delay, and accuracy per classi cation for the MNIST and CIFAR-10 datasets, and compared our networks and architecture with other algorithms and architectures [14,18,28,41,50,59] that address the same problem. For the MNIST dataset, at iso-accuracy, our results demonstrate an 8.7× improvement in energy-delay product (EDP) when compared with a state-of-the-art accelerator.…”

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confidence: 99%

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A Mixed Signal Architecture for Convolutional Neural Networks

Lou

Pan²,

McGuinness

et al. 2019

J. Emerg. Technol. Comput. Syst.

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Deep neural network (DNN) accelerators with improved energy and delay are desirable for meeting the requirements of hardware targeted for IoT and edge computing systems. Convolutional neural networks (CoNNs) belong to one of the most popular types of DNN architectures. is paper presents the design and evaluation of an accelerator for CoNNs. e system-level architecture is based on mixed-signal, cellular neural networks (CeNNs). Speci cally, we present (i) the implementation of di erent layers, including convolution, ReLU, and pooling, in a CoNN using CeNN, (ii) modi ed CoNN structures with CeNN-friendly layers to reduce computational overheads typically associated with a CoNN, (iii) a mixed-signal CeNN architecture that performs CoNN computations in the analog and mixed signal domain, and (iv) design space exploration that identi es what CeNN-based algorithm and architectural features fare best compared to existing algorithms and architectures when evaluated over common datasets -MNIST and CIFAR-10. Notably, the proposed approach can lead to 8.7× improvements in energy-delay product (EDP) per digit classi cation for the MNIST dataset at iso-accuracy when compared with the state-of-the-art DNN engine, while our approach could o er 4.3× improvements in EDP when compared to other network implementations for the CIFAR-10 dataset.When considering application-speci c hardware to support neural networks, it is important that said hardware can implement networks that can be extensible to a large class of networks, and solve a large collection of application-level problems. Deep neural networks (DNNs) represent a class of such networks and have demonstrated their strength in applications such as playing the game of Go [54], image and video analysis [32], target tracking [31], etc. In this paper, we use convolutional neural network (CoNN) as a case study for DNNs due to its general prevalence. CoNNs are computationally intensive, which could lead to high latency and energy for inference and even higher latency/energy for training. e focus of this paper is on developing a low energy/delay mixed-signal system based on cellular neural networks (CeNNs) for realizing CoNN.A Cellular Nonlinear/Neural Network (CeNN) is an analog computing architecture [11] that could be well suited for many information processing tasks. In a CeNN, identical processing units (called cells) process analog information in a concurrent manner. Interconnection between cells is typically local (i.e., nearest neighbor) and space-invariant. For spatio-temporal applications, CeNNs can o er vastly superior performance and power e ciency when compared to conventional von Neumann architectures [47,61]. Using "CeNNs for CoNN" allows the bulk of the computation associated with a CoNN to be performed in the analog domain. Sensed information could immediately be processed with no analog-to-digital conversion (ADC). Also, inference-based processing tasks can tolerate lower precision (e.g., Google's TPU employs 8-bit integer matrix multiplies [24]) typically associa...

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A 640M pixel/s 3.65mW sparse event-driven neuromorphic object recognition processor with on-chip learning

Cited by 61 publications

References 3 publications

A 0.086-mm<formula> <tex>$^2$</tex> </formula> 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOS

A 0.086-mm<formula> <tex>$^2$</tex> </formula> 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOS

MorphIC: A 65-nm 738k-Synapse/mm$^2$ Quad-Core Binary-Weight Digital Neuromorphic Processor With Stochastic Spike-Driven Online Learning

A Mixed Signal Architecture for Convolutional Neural Networks

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