“…In the past 5 years, the pixel pitch of CMOS image sensors (CIS) has shrunk from 0.9 μm to 0.56 μm [ 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 ] at a fast pace of almost one generation every year. Despite the pixel design and process development effort to maintain the quantum efficiency (QE) and the full well capacity (FWC) at comparable levels across the generations, the smaller pixels still face the fundamental physical challenge: under a given scene illumination and integration time, the number of photons that can be captured by smaller pixels is inevitably less.…”