A 65-nm CMOS Low Dropout Regulator Featuring &gt;60-dB PSRR Over 10-MHz Frequency Range and 100-mA Load Current Range

Jiang, Jin; Shu, Wei; Chang, Joseph S.

doi:10.1109/jssc.2018.2837044

Cited by 70 publications

(25 citation statements)

References 18 publications

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“…The requirements of the LDO in thermo-optical tuning are different from traditional designs. Most conventional LDOs are specifically designed for SoCs that require a wellregulated output in a wide load range [8], [9]. By contrast, the LDO in thermo-optical tuning should provide a dynamic output to a fixed resistive load.…”

Section: Tops and Power Management Circuitmentioning

confidence: 99%

A Four-Channel Gray-Code Addressing TDM Clocked-Analog LDO for Thermo-Optic Tuning in Silicon Photonics

ye¹,

Ye²,

Tan³

2021

Preprint

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This paper presents a Gray-code addressing time division multiplexing (TDM) clocked-analog low-dropout regulator (CLDO) that shares one controller between four output channels with only one compensation capacitor. We apply the Gray-code addressing strategy to reduce the crosstalk. We also apply the split-output amplifier structure to share the compensation capacitor for further chip area reduction. In addition, we introduce a lightweight local-generated supply to increase the dynamic range. Implemented in 130 nm CMOS process, this design has a total chip area of 0.056 mm2 , which is 67.5% smaller than the conventional solution with four identical LDOs. Post layout simulation results show that the presented four-channel TDM CLDO can simultaneously track four 1 V<sub>pp</sub> sinusoidal signals at different frequencies with negligible crosstalk. This TDM CLDO is a promising solution for supplying multiple thermo-optic phase shifters (TOPSs) in silicon photonics

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Section: Tops and Power Management Circuitmentioning

confidence: 99%

A Four-Channel Gray-Code Addressing TDM Clocked-Analog LDO for Thermo-Optic Tuning in Silicon Photonics

ye¹,

Ye²,

Tan³

2021

Preprint

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“…Note that oscillators with better phase noise (i.e., higher Q or P DC ) impose even more stringent noise requirements on their supply voltage. 1 Note that the reported spot noise of LDOs with high current efficiency (i.e., > 90%) is much higher than the supply noise tolerated by the oscillator [11], [12], [28], [29]. To reduce the output noise of the LDO, its quiescent current should be increased, which leads to a severe current efficiency degradation (e.g., 70% in [30]) or an external filtering capacitor must be used [8].…”

Section: A Supply Noise Requirementsmentioning

confidence: 99%

A Switched-Capacitor DC-DC Converter Powering an LC Oscillator to Achieve 85% System Peak Power Efficiency and −65dBc Spurious Tones

Urso

Chen

Staszewski

et al. 2020

IEEE Trans. Circuits Syst. I

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In this paper, we propose a new scheme to directly power a 4.9-5.6 GHz LC oscillator from a recursive switched-capacitor DC-DC converter. A finite-state machine is integrated to automatically adjust the conversion ratio and switching frequency of the converter such that its DC output voltage is within ±5% of the desired 1V across input voltage range 1.3-2.2 V and <2 mA load current conditions. A gate-driver circuit is embedded in each switch of the converter to guarantee constant on-resistance across PVT variations without sacrificing device reliability. Furthermore, a spur reduction block (SRB) is embedded in the oscillator to suppress the ripple induced spurs by stabilizing its tail current. Both the converter and the oscillator are implemented in 40-nm CMOS technology. The measured peak power efficiency of the converter is 87%, while its spot noise is <1.5 nV/ √ Hz, which does not degrade the phase noise of the oscillator. The SRB suppresses the spur to < −65 dBc under the 30 mV pp ripple of the converter.

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“…As supply voltages are decreasing, advanced systems on chip (SOCs) employ increasingly lower voltage supplies, high operation speed and in part by the ever-decreasing feature size of CMOS fabrication process [1]. Further as supply voltages are decreasing and also ensuing reduced signal swing, ripple on the power supply lines start playing a dominant role in noisesensitive analog blocks such as ADCs, PLLs and RF-SOCs [2].…”

Section: Introductionmentioning

confidence: 99%

Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

Patel¹

2021

Preprint

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Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

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A 65-nm CMOS Low Dropout Regulator Featuring >60-dB PSRR Over 10-MHz Frequency Range and 100-mA Load Current Range

Cited by 70 publications

References 18 publications

A Four-Channel Gray-Code Addressing TDM Clocked-Analog LDO for Thermo-Optic Tuning in Silicon Photonics

A Four-Channel Gray-Code Addressing TDM Clocked-Analog LDO for Thermo-Optic Tuning in Silicon Photonics

A Switched-Capacitor DC-DC Converter Powering an LC Oscillator to Achieve 85% System Peak Power Efficiency and −65dBc Spurious Tones

Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

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