A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation

Devlin, Benjamin; Ikeda, Makoto; Asada, Kunihiro

doi:10.1109/jssc.2011.2164024

Cited by 10 publications

(2 citation statements)

References 22 publications

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“…Asynchronous FPGAs developed by Cornell University [4], [5], Achronix [6] and the University of Tokyo [7] employ finegrained pipelined architecture to achieve high throughput. References [8]- [10] propose asynchronous FPGA architecture focusing on low power consumption.…”

Section: Introductionmentioning

confidence: 99%

Architecture of an Asynchronous FPGA for Handshake-Component-Based Design

Yoshiya

Hariyama

Kameyama

2013

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper presents a novel architecture of an asynchronous FPGA for handshake-component-based design. The handshakecomponent-based design is suitable for large-scale, complex asynchronous circuit because of its understandability. This paper proposes an areaefficient architecture of an FPGA that is suitable for handshake-componentbased asynchronous circuit. Moreover, the Four-Phase Dual-Rail encoding is employed to construct circuits robust to delay variation because the data paths are programmable in FPGA. The FPGA based on the proposed architecture is implemented in a 65 nm process. Its evaluation results show that the proposed FPGA can implement handshake components efficiently.

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Section: Introductionmentioning

confidence: 99%

Architecture of an Asynchronous FPGA for Handshake-Component-Based Design

Yoshiya

Hariyama

Kameyama

2013

IEICE Trans. Inf. & Syst.

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“…SFQ logic can enhance clock frequency because voltagepulse logic with fast (10 −12 s) and low-energy (10 −19 J) switching of Josephson junctions (JJs) mitigates the powerwall problems. For example, a recent study showed that an SFQ-based neural-network accelerator based on a currently available 1.0 μm process 8) operated at 52.6 GHz and 1.9 W, 9) whereas a CMOS-based neural-network accelerator operated at 0.7 GHz and 40 W. 10) Gate-level pipelining 11,12) can maximize throughput of SFQ circuits. Unlike CMOS logic circuits, additional pipeline registers are unnecessary because SFQ logic gates are clocked gates with latch functions.…”

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confidence: 99%

Investigation of timing margin in single-flux-quantum 4 bit adders for increasing clock frequency of gate-level-pipelined circuits

Nagaoka,

Nakano,

Kashima

et al. 2024

Appl. Phys. Express

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This study investigates the timing margin required to handle fluctuations and variations in superconductor single-flux-quantum gate-level-pipelined adders; a smaller timing margin would improve the clock frequencies of gate-level-pipelined circuits. To evaluate timing margins, we demonstrated three 4-bit adders with 50-, 75-, and 100-GHz target clock frequencies using a 1.0-μm process. We estimated that the required timing margin of the adders was 2.1 ps. This indicates that previously reported gate-level-pipelined circuits operating at 30–60 GHz could operate at higher clock frequencies by reducing the timing margins.

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