A 65nm 0.6–1.2V Low-Dropout Regulator Using Voltage-Difference-to-Time Converter With Direct Output Feedback

Shin, Kwanghyun; Jee, Dong-Woo; Jeon, D.

doi:10.1109/tcsii.2020.3007760

Cited by 10 publications

(9 citation statements)

References 11 publications

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“…One important parameter that is used to evaluate the performance of a switching converter is known as efficiency enhancement factor (EEF) which is defined based on linear regulators 17 . Low‐dropout (LDO) voltage regulator, specially capacitorless LDO, is appropriate topology for integrating power supply on chip because of its low occupied area 37–39 . For instance, in previous studies, 37–39 the current density is 3125, 723, and 377 mA/mm 2 , respectively.…”

Section: Simulation Resultsmentioning

confidence: 99%

Fully integrated switched‐inductor switched‐capacitor dual‐path DC–DC converter

Meshkat

Dehghani

Farzanehfard

2022

Circuit Theory & Apps

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A fully integrated switched-inductor switched-capacitor (SISC) DC-DC converter is proposed. This converter is designed in such a way that the input voltage can be twice the process allowable voltage without damaging the on-chip transistors. To mitigate large series resistance of on-chip inductors as one of the main challenges in the switched-inductor power supply on chip, two solutions are proposed. By using analytical model of an on-chip inductor, optimal physical dimensions are designed to achieve the desired inductance with minimum series resistance in a small area. Along with the optimization, the dualpath structure of the proposed converter reduces series resistance losses of the on-chip inductor and increases the effective quality factor up to 7 times in duty cycle of 0.8. The proposed converter is implemented in 0.18 μm standard CMOS process. The circuit converts input voltage of 3.6-0.9 V at the load current of 125 mA with the efficiency of 72.8%. Efficiency enhancement factor reaches 72% at 600 mV output voltage. The achieved current density of the proposed converter is 333 mA/mm 2 . By calculating small signal model of the proposed converter and designing a suitable feedback loop, an appropriate transient behavior was provedcascode buck converter, fully integrated voltage regulator, high current density, high stepdown, inductor quality factor boosting, on-chip inductor optimum design

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Section: Simulation Resultsmentioning

confidence: 99%

Fully integrated switched‐inductor switched‐capacitor dual‐path DC–DC converter

Meshkat

Dehghani

Farzanehfard

2022

Circuit Theory & Apps

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“…The calculation of figure of merit (FOM) is widely adopted by researchers and acts as a collective measure of all other performance parameters. The most established equation for calculating FOM is included in Equation (7), which is adopted by many researchers [19][20][21][22][23]45,47,48,[51][52][53][54][55][56][57][58]60,62]. Moreover, several methods of evaluating FOM is presented by authors to signify their design performances, which are added in Equation ( 8) [25], Equation (9) [44], Equation (10) [58], Equation (11) [59], Equation (12) [51], and Equation ( 13) [48].…”

Section: Figure Of Merit (Fom)mentioning

confidence: 99%

“…The necessary quiescent current is the minimum value, which is only 0.016 µA [45]. One design offers the minimum low-dropout voltage along with the maximum current efficiency [51]. There are a few other parameters such as dropout voltage and current efficiency that define the overall performance of LDO.…”

Section: Performance Comparison Of Aldomentioning

confidence: 99%

“…Therefore, the designer introduced a negative charge pump in the controller section to extend the voltage range of the error amplifier. Similarly, the design in [51] achieved a target of low voltage operation by using a different technique of a voltage to time converter with direct output feedback. On the other hand, the focus of design [49] was to achieve clean power by suppressing ripples, which is accomplished by adapting the concept of the multistage error amplifier.…”

Section: Performance Comparison Of Aldomentioning

confidence: 99%

“…Voltage Difference to Time Converter with Direct Output FeedbackA low-dropout regulator scheme modeled based on a voltage difference to time converter (VDTC) was reported byShin et al (2020), as given in Figure23[51]. Extracting attributes from both digital and analog LDOs, the design yields a ripple-free output and small quiescent current over a broad range of operating voltage.…”

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confidence: 99%

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CMOS Low-Dropout Voltage Regulator Design Trends: An Overview

et al. 2022

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Systems-on-Chip’s (SoC) design complexity demands a high-performance linear regulator architecture to maintain a stable operation for the efficient power management of today’s devices. Over the decades, the low-dropout (LDO) voltage regulator design has gained attention due to its design scalability with better performance in various application domains. Industry professionals as well as academia have put forward their innovations such as event-driven explicit time-coding, exponential-ratio array, switched RC bandgap reference circuit, etc., to make a trade-off between several performance parameters such as die area, ripple rejection, supply voltage range, and current efficiency. However, current LDO architectures in micro and nanometer complementary metal–oxide–semiconductor (CMOS) technology face some challenges, such as short channel effects, gate leakage, fabrication difficulty, and sensitivity to process variations at nanoscale. This review presents the LDO architectures, optimization techniques, and performance comparisons in different LDO design domains such as digital, analog, and hybrid. In this review, various state-of-the-art circuit topologies, deployed for the betterment of LDO performance and focusing on the specific parameter up-gradation to the overall improvement of the functionality, are framed, which will serve as a comparative study and reference for researchers.

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