A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing

Kushwaha, Dinesh; Sharma, Aditya; Gupta, Neha; Raj, Ritik; Joshi, Amit; Mishra, Jwalant; Kohli, Rajat; Miryala, Sandeep; Joshi, Rajiv V.; Dasgupta, S.; Bulusu, Anand

doi:10.1109/iscas48785.2022.9937908

Cited by 10 publications

References 23 publications

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Capacitance and Conductance Compensation Methods for Efficient Computing‐In‐Memory Designs

Luo,

Qiao,

Sun

2024

Adv Elect Materials

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Compensation has been a common while unacknowledged strategy in the design of computing‐in‐memory (CIM) schemes. It enables efficient CIM designs by intentionally letting the sum of capacitances or conductances of two or more rows or columns in the memory array equal, thus resulting in a concise mathematical formula regarding the memory cell data and the input data, which constitute computing primitives. Here, the capacitance and conductance compensation methods are reviewed that have been used for CIM designs based on static random‐access memory (SRAM) in combination with capacitors and nonvolatile resistive memory, respectively, and uncover the underlying principles and their application to CIM. It is hoped this effort will help recognize the compensation methods as a building block for CIM designs, and will be an inspiration to developing more CIM schemes that are more compact in area, more efficient in energy consumption, and capable of solving more complicated problems.

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Capacitance and Conductance Compensation Methods for Efficient Computing‐In‐Memory Designs

Luo,

Qiao,

Sun

2024

Adv Elect Materials

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8T-SRAM Based Process-In-Memory (PIM) System With Current Mirror for Accurate MAC Operation

Chung,

Kim,

et al. 2024

IEEE Access

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Process-in-memory (PIM) is an emerging computing paradigm to overcome the energy bottleneck inherent in conventional computing platform. While PIM utilizes several types of memory elements, SRAM based PIM has been researched extensively for its high scalability and feasibility by using CMOS process technology. In this work, we proposed 8T SRAM based Process-in-memory system with current mirror for accurate MAC operation. To resolve the nonlinearity issue inherent in current-based SRAM MAC macro, we utilized cascaded current mirror. Furthermore, to enable more precise MAC operation, we allocated RWL timing pulses which drive 8T SRAM bitcells in the middle of timing duration. Our PIM architecture realize 4 bit input, 4 bit weight and 4 bit output precisions. Prototype chip has been fabricated using TSMC 65nm GP process technology. Measurement result has proved the MAC operation linearity of designed 8T SRAM based PIM system, and its throughput and energy efficiency with 0.29 GOPS and 1.05 TOPS/W. Software level analysis proved that our design can achieve upto 98.02 percent accuracy for MNIST dataset classification and 94.93 percent accuracy for CIFAR-10 dataset classification.INDEX TERMS Processing-in-memory (PIM), current-mode accumulation, current mirror, Multiply-and-Accumulate (MAC), multi-bit computing, static random access memory (SRAM)

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A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application

Kushwaha

Kohli

Mishra

et al. 2023

2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)

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A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing

Cited by 10 publications

References 23 publications

Capacitance and Conductance Compensation Methods for Efficient Computing‐In‐Memory Designs

Capacitance and Conductance Compensation Methods for Efficient Computing‐In‐Memory Designs

8T-SRAM Based Process-In-Memory (PIM) System With Current Mirror for Accurate MAC Operation

A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application

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