A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die

New e-fuse device conceptWe have developed a novel e-fuse technology utilizing a Fig. 1 shows the schematic of three types of e-fuse: a Cu-via for the first time. Due to its unique structure and gate-electrode-fuse, a Cu-fuse, and a via-fuse. Silicided gate crack-assisted mechanism, void formation locations can be poly-Si is commonly used as the fuse material of the effectively confined to the via-metal interface, enabling gate-electrode-fuse, and will be replaced by metal in the highly stable operation as well as a large on-off ratio of 7 32nm node and beyond. However, such metal is not suitable orders of magnitude. We have confirmed a sub-iOppm for a blown material. We therefore proposed the use of Cu initial-failure rate and a sub-20ppm failure rate after thermal wire for the e-fuse material. A sufficiently large void in the stability test equivalent to the thermal stress during the wire enables Cu wire to be used as an e-fuse device. A large practical packaging process.We believe that this resistance change could also be obtained using Cu-wire. Fig. technology is indispensable for the 32nm technology node 2 shows an example of a programmed Cu-fuse with such a and beyond, where metal material is commonly used as a void (3). However, the Cu-fuse (wire-fuse) has the poly-gate, rendering it unsuitable for fuse devices.previously mentioned problem in the area of reliability. To solve this problem, we have proposed using a Cu-via for the Introduction e-fuse material instead of the wire. The greatest merit of using a via as the fuse is the ability to confine the location of OTP (one time programmable) devices are becoming the void formation. indispensable for applications such as security key encryption, memory redundancy, characteristic trimming (i.e., LCD Via-fuse characteristics

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An Adaptive Design of SRAM Memory Cell

Ishibashi

2007

2007 IEEE International Electron Devices Meeting

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A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die

Cited by 4 publications

References 18 publications

Review of fuse and antifuse solutions for advanced standard CMOS technologies

Review of fuse and antifuse solutions for advanced standard CMOS technologies

A Novel Via-fuse Technology Featuring Highly Stable Blow Operation with Large On-off Ratio for 32nm Node and Beyond

An Adaptive Design of SRAM Memory Cell

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