A 65nm Sub-V_t Microcontroller with Integrated SRAM and Switched-Capacitor DC-DC Converter

Abstract

Aggressive supply voltage scaling to below the device threshold voltage provides significant energy and leakage power reduction in logic and SRAM circuits. Consequently, it is a compelling strategy for energy-constrained systems with relaxed performance requirements. However, effects of process variation become more prominent at low voltages, particularly in deeply scaled technologies. This paper presents a 65 nm system-on-a-chip which demonstrates techniques to mitigate variation, enabling sub-threshold operation down to 300 mV. A 16-bit microcontroller core is designed with a custom sub-threshold cell library and timing methodology to address output voltage failures and propagation delays in logic gates. A 128 kb SRAM employs an 8 T bit-cell to ensure read stability, and peripheral assist circuitry to allow sub-reading and writing. The logic and SRAM function in the range of 300 mV to 600 mV, consume 27.2 pJ/cycle at the optimal DD of 500 mV, and 1 W standby power at 300 mV. To supply variable voltages at these low power levels, a switched capacitor DC-DC converter is integrated on-chip and achieves above 75% efficiency while delivering between 10 W to 250 W of load power.

Sub-Threshold Standard Cell Sizing Methodology and Library Comparison

“…In [3,4], the authors calculate the optimum supply voltage to minimize energy consumption. It is also claimed that, theoretically, minimum sized cells are optimal for energy reduction.…”

“…Particularly interesting is a closed form current equation derived for stacked transistors in relation to other transistors in the same stack. Compared to [3,4,9], our sizing approach focuses on narrowing the current/delay distribution spread and on increasing the performance through a new balancing theory that slows down fast transistors and vice versa. In [8], the transistor reverse short channel effect (RSCE) is used for device sizing optimization, where the channel length is increased to have an optimal threshold voltage which makes the transistors have a higher current, be less sensitive to random variations, and to have a smaller area.…”

“…More and more systems with low performance requirements are operated from a near/sub-threshold supply voltage in order to save power [3][4][5][6][7]. However, due to the fact that the gate voltage drive of the transistors operating in the sub-threshold domain is small, standard logic cells become more sensitive to process variations.…”

An Accelerator-Based Wireless Sensor Network Processor in 130 nm CMOS

“…Unfortunately, subthreshold operation increases susceptibility to on-die parameter variations, limits the performance needed for real-time applications, and requires custom SRAM design [9]. In order to accommodate the wide variety of computing needs in WSNs while minimizing energy consumption, we propose an accelerator-based system architecture.…”

Variation resilient adaptive controller for subthreshold circuits

“…Over the last couple of years there has been considerable progress in designing subthreshold circuits and architectures that operate with supply voltages (V dd ) well below the transistor threshold voltage (V th ) and with minimum computation energy. Recent examples include a 3.5 pJ inst processor [1], a 27.3 pJ inst microcontroller [2], 180mV FFT processor [3] and 1.33 pJ sample FIR filter [4]. Most of the recent research efforts in the area of subthreshold logic has been focusing on addressing variability [5] [6].…”